From 31ded07abc024811c48fd0b7b2378841065ac2bf Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 24 Mar 2022 20:35:46 +0000
Subject: [PATCH] check ulx3s, add CRG support for ulx3s

---
 src/crg.py | 27 ++++++++++++++++++---------
 src/ls2.py |  6 ++++--
 2 files changed, 22 insertions(+), 11 deletions(-)

diff --git a/src/crg.py b/src/crg.py
index f7baa0a..1141b26 100644
--- a/src/crg.py
+++ b/src/crg.py
@@ -11,7 +11,7 @@
 
 
 from nmigen import (Elaboratable, Module, Signal, ClockDomain, Instance,
-                    ClockSignal, ResetSignal)
+                    ClockSignal, ResetSignal, Const)
 
 __ALL__ = ["ECPIX5CRG"]
 
@@ -175,13 +175,17 @@ class ECPIX5CRG(Elaboratable):
         m = Module()
 
         # Get 100Mhz from oscillator
-        clk100 = platform.request("clk100")
+        extclk = platform.request(platform.default_clk)
         cd_rawclk = ClockDomain("rawclk", local=True, reset_less=True)
-        m.d.comb += cd_rawclk.clk.eq(clk100)
+        m.d.comb += cd_rawclk.clk.eq(extclk)
         m.domains += cd_rawclk
 
         # Reset
-        reset = platform.request(platform.default_rst).i
+        if platform.default_rst is not None:
+            reset = platform.request(platform.default_rst).i
+        else:
+            reset = Const(0) # whoops
+
         gsr0 = Signal()
         gsr1 = Signal()
 
@@ -198,22 +202,26 @@ class ECPIX5CRG(Elaboratable):
                              i_GSR=gsr1),
         ]
 
+        # PLL
+        m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~reset)
+
         # Power-on delay (655us)
-        podcnt = Signal(3, reset=-1)
+        podcnt = Signal(18, reset=-1)
         pod_done = Signal()
-        with m.If(podcnt != 0):
+        with m.If((podcnt != 0) & pll.locked):
             m.d.rawclk += podcnt.eq(podcnt-1)
         m.d.rawclk += pod_done.eq(podcnt == 0)
 
-        # Generating sync2x (200Mhz) and init (25Mhz) from clk100
+        # Generating sync2x (200Mhz) and init (25Mhz) from extclk
         cd_sync2x = ClockDomain("sync2x", local=False)
         cd_sync2x_unbuf = ClockDomain("sync2x_unbuf",
                                       local=False, reset_less=True)
         cd_init = ClockDomain("init", local=False)
         cd_sync = ClockDomain("sync", local=False)
         cd_dramsync = ClockDomain("dramsync", local=False)
-        m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~reset)
-        pll.set_clkin_freq(100e6)
+
+        # create PLL clocks
+        pll.set_clkin_freq(platform.default_clk_frequency)
         pll.create_clkout(ClockSignal("sync2x_unbuf"), 2*self.sys_clk_freq)
         pll.create_clkout(ClockSignal("init"), 25e6)
         m.submodules += Instance("ECLKSYNCB",
@@ -244,3 +252,4 @@ class ECPIX5CRG(Elaboratable):
         m.d.comb += ClockSignal("dramsync").eq(ClockSignal("sync"))
 
         return m
+
diff --git a/src/ls2.py b/src/ls2.py
index 0ecc9ce..e4a7188 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -271,7 +271,7 @@ class DDR3SoC(SoC, Elaboratable):
             firmware = "firmware/main.bin"
 
         # set up clock request generator
-        if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
+        if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s']:
             self.crg = ECPIX5CRG(clk_freq)
         if fpga in ['arty_a7']:
             self.crg = ArtyA7CRG(clk_freq)
@@ -587,7 +587,9 @@ def build_platform(fpga, firmware):
     if fpga == 'versa_ecp5_85':
         clk_freq = 55e6
     if fpga == 'arty_a7':
-        clk_freq = 25e6
+        clk_freq = 50e6
+    if fpga == 'ulx3s':
+        clk_freq = 12.5e6
 
     # select a firmware address
     fw_addr = None
-- 
2.30.2