From 31e910b9234f84bb4fd847657e52a724611961d6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 15 Jul 2020 14:13:28 +0100 Subject: [PATCH] select RA based on LDSTMode.update in PowerDecode2 --- src/soc/decoder/power_decoder2.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 85a8c089..06bdf14e 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -18,7 +18,7 @@ from soc.decoder.power_decoder import create_pdecode from soc.decoder.power_enums import (MicrOp, CryIn, Function, CRInSel, CROutSel, LdstLen, In1Sel, In2Sel, In3Sel, - OutSel, SPR, RC) + OutSel, SPR, RC, LDSTMode) from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data from soc.consts import MSR @@ -361,7 +361,7 @@ class DecodeOut2(Elaboratable): comb = m.d.comb # update mode LD/ST uses read-reg A also as an output - with m.If(self.dec.op.upd): + with m.If(self.dec.op.upd == LDSTMode.update): comb += self.reg_out.eq(self.dec.RA) comb += self.reg_out.ok.eq(1) -- 2.30.2