From 31f35c4fc55da1fc4f5de8713100299e49f65d8d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 Jun 2019 14:19:03 +0100 Subject: [PATCH] split out reg table format --- simple_v_extension/abridged_spec.mdwn | 24 +----------------------- simple_v_extension/reg_table_format.mdwn | 24 ++++++++++++++++++++++++ simple_v_extension/specification.mdwn | 24 +----------------------- 3 files changed, 26 insertions(+), 46 deletions(-) create mode 100644 simple_v_extension/reg_table_format.mdwn diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn index c54884dec..719f7c587 100644 --- a/simple_v_extension/abridged_spec.mdwn +++ b/simple_v_extension/abridged_spec.mdwn @@ -155,29 +155,7 @@ Note: CSRRC and other bitsetting may still be used, they are however not particu The purpose of the Register table is to mark which registers change behaviour if used in a "Standard" (normally scalar) opcode. -16 bit format: - -| RegCAM | 15 | (14..8) | 7 | (6..5) | (4..0) | -| ------ | - | - | - | ------ | ------- | -| 0 | isvec0 | regidx0 | i/f | vew0 | regkey | -| 1 | isvec1 | regidx1 | i/f | vew1 | regkey | -| 2 | isvec2 | regidx2 | i/f | vew2 | regkey | -| 3 | isvec3 | regidx3 | i/f | vew3 | regkey | - -8 bit format: - -| RegCAM | | 7 | (6..5) | (4..0) | -| ------ | | - | ------ | ------- | -| 0 | | i/f | vew0 | regnum | - -Mapping the 8-bit to 16-bit format: - -| RegCAM | 15 | (14..8) | 7 | (6..5) | (4..0) | -| ------ | - | - | - | ------ | ------- | -| 0 | isvec=1 | regnum0<<2 | i/f | vew0 | regnum0 | -| 1 | isvec=1 | regnum1<<2 | i/f | vew1 | regnum1 | -| 2 | isvec=1 | regnum2<<2 | i/f | vew2 | regnum2 | -| 3 | isvec=1 | regnum2<<2 | i/f | vew3 | regnum3 | +[[!inline raw="yes" pages="simple_v_extension/reg_table_format" ]] Fields: diff --git a/simple_v_extension/reg_table_format.mdwn b/simple_v_extension/reg_table_format.mdwn new file mode 100644 index 000000000..35a460828 --- /dev/null +++ b/simple_v_extension/reg_table_format.mdwn @@ -0,0 +1,24 @@ +16 bit format: + +| RegCAM | | 15 | (14..8) | 7 | (6..5) | (4..0) | +| ------ | | - | - | - | ------ | ------- | +| 0 | | isvec0 | regidx0 | i/f | vew0 | regkey | +| 1 | | isvec1 | regidx1 | i/f | vew1 | regkey | +| .. | | isvec.. | regidx.. | i/f | vew.. | regkey | +| 15 | | isvec15 | regidx15 | i/f | vew15 | regkey | + +8 bit format: + +| RegCAM | | 7 | (6..5) | (4..0) | +| ------ | | - | ------ | ------- | +| 0 | | i/f | vew0 | regnum | + +Showing the mapping (relationship) between 8-bit and 16-bit format: + +| RegCAM | 15 | (14..8) | 7 | (6..5) | (4..0) | +| ------ | - | - | - | ------ | ------- | +| 0 | isvec=1 | regnum0<<2 | i/f | vew0 | regnum0 | +| 1 | isvec=1 | regnum1<<2 | i/f | vew1 | regnum1 | +| 2 | isvec=1 | regnum2<<2 | i/f | vew2 | regnum2 | +| 3 | isvec=1 | regnum2<<2 | i/f | vew3 | regnum3 | + diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 53d9837af..a36234338 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -505,29 +505,7 @@ anywhere to the *full* 128 register range. Thus, RVC becomes far more powerful and has many more opportunities to reduce code size that in Standard RV32/RV64 executables. -16 bit format: - -| RegCAM | | 15 | (14..8) | 7 | (6..5) | (4..0) | -| ------ | | - | - | - | ------ | ------- | -| 0 | | isvec0 | regidx0 | i/f | vew0 | regkey | -| 1 | | isvec1 | regidx1 | i/f | vew1 | regkey | -| .. | | isvec.. | regidx.. | i/f | vew.. | regkey | -| 15 | | isvec15 | regidx15 | i/f | vew15 | regkey | - -8 bit format: - -| RegCAM | | 7 | (6..5) | (4..0) | -| ------ | | - | ------ | ------- | -| 0 | | i/f | vew0 | regnum | - -Showing the mapping (relationship) between 8-bit and 16-bit format: - -| RegCAM | 15 | (14..8) | 7 | (6..5) | (4..0) | -| ------ | - | - | - | ------ | ------- | -| 0 | isvec=1 | regnum0<<2 | i/f | vew0 | regnum0 | -| 1 | isvec=1 | regnum1<<2 | i/f | vew1 | regnum1 | -| 2 | isvec=1 | regnum2<<2 | i/f | vew2 | regnum2 | -| 3 | isvec=1 | regnum2<<2 | i/f | vew3 | regnum3 | +[[!inline raw="yes" pages="simple_v_extension/reg_table_format" ]] i/f is set to "1" to indicate that the redirection/tag entry is to be applied to integer registers; 0 indicates that it is relevant to -- 2.30.2