From 3201554f7646e8cbd007124104ee5198a1dbb83d Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 23 Jan 2013 15:13:06 +0100 Subject: [PATCH] fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert() --- migen/fhdl/verilog.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index b26689d5..1c4d6082 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -279,11 +279,13 @@ def _printinit(f, ios, ns): r += "end\n\n" return r -def convert(f, ios=set(), name="top", +def convert(f, ios=None, name="top", clock_domains=None, return_ns=False, memory_handler=verilog_mem_behavioral.handler, display_run=False): + if ios is None: + ios = set() if clock_domains is None: clock_domains = dict() for d in f.get_clock_domains(): -- 2.30.2