From 3231d64b5e3e4e600f983acb7213bd9b39ddfad3 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Wed, 15 Mar 2017 21:17:35 +0000 Subject: [PATCH] re PR target/79038 (Improve PowerPC ISA 3.0 conversion between integers and hardware _Float128) [gcc] 2017-03-15 Michael Meissner PR target/79038 * config/rs6000/rs6000.md (float2): Define insns to convert from signed/unsigned char/short to IEEE 128-bit floating point. (floatuns2): Likewise. [gcc/testsuite] 2017-03-15 Michael Meissner PR target/79038 * gcc.target/powerpc/pr79038-1.c: New test. From-SVN: r246178 --- gcc/ChangeLog | 8 +++ gcc/config/rs6000/rs6000.md | 69 ++++++++++++++++++++ gcc/testsuite/ChangeLog | 5 ++ gcc/testsuite/gcc.target/powerpc/pr79038-1.c | 39 +++++++++++ 4 files changed, 121 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr79038-1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 13c5c0df2e1..c01d583faed 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-03-15 Michael Meissner + + PR target/79038 + * config/rs6000/rs6000.md (float2): Define + insns to convert from signed/unsigned char/short to IEEE 128-bit + floating point. + (floatuns2): Likewise. + 2017-03-15 Uros Bizjak PR target/80019 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 466075a8c75..000d84033c3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -14467,6 +14467,43 @@ operands[2] = gen_reg_rtx (DImode); }) +(define_insn_and_split "float2" + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v,v,v") + (float:IEEE128 (match_operand:QHI 1 "nonimmediate_operand" "v,r,Z"))) + (clobber (match_scratch:DI 2 "=X,r,X"))] + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + rtx dest_di = gen_rtx_REG (DImode, REGNO (dest)); + + if (altivec_register_operand (src, mode)) + emit_insn (gen_extenddi2 (dest_di, src)); + else if (int_reg_operand (src, mode)) + { + rtx ext_di = operands[2]; + emit_insn (gen_extenddi2 (ext_di, src)); + emit_move_insn (dest_di, ext_di); + } + else if (MEM_P (src)) + { + rtx dest_qhi = gen_rtx_REG (mode, REGNO (dest)); + emit_move_insn (dest_qhi, src); + emit_insn (gen_extenddi2 (dest_di, dest_qhi)); + } + else + gcc_unreachable (); + + emit_insn (gen_float_di2_hw (dest, dest_di)); + DONE; +} + [(set_attr "length" "8,12,12") + (set_attr "type" "vecfloat") + (set_attr "size" "128")]) + (define_insn "floatuns_di2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unsigned_float:IEEE128 @@ -14493,6 +14530,38 @@ operands[2] = gen_reg_rtx (DImode); }) +(define_insn_and_split "floatuns2" + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v,v,v") + (unsigned_float:IEEE128 + (match_operand:QHI 1 "nonimmediate_operand" "v,r,Z"))) + (clobber (match_scratch:DI 2 "=X,r,X"))] + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + rtx dest_di = gen_rtx_REG (DImode, REGNO (dest)); + + if (altivec_register_operand (src, mode) || MEM_P (src)) + emit_insn (gen_zero_extenddi2 (dest_di, src)); + else if (int_reg_operand (src, mode)) + { + rtx ext_di = operands[2]; + emit_insn (gen_zero_extenddi2 (ext_di, src)); + emit_move_insn (dest_di, ext_di); + } + else + gcc_unreachable (); + + emit_insn (gen_floatuns_di2_hw (dest, dest_di)); + DONE; +} + [(set_attr "length" "8,12,8") + (set_attr "type" "vecfloat") + (set_attr "size" "128")]) + ;; IEEE 128-bit instructions with round to odd semantics (define_insn "*truncdf2_odd" [(set (match_operand:DF 0 "vsx_register_operand" "=v") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e5ebdc69371..3ca7b5fc483 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-03-15 Michael Meissner + + PR target/79038 + * gcc.target/powerpc/pr79038-1.c: New test. + 2017-03-15 Segher Boessenkool PR fortran/33271 diff --git a/gcc/testsuite/gcc.target/powerpc/pr79038-1.c b/gcc/testsuite/gcc.target/powerpc/pr79038-1.c new file mode 100644 index 00000000000..0b1fa5d87bd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr79038-1.c @@ -0,0 +1,39 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2 -mfloat128" } */ + +#ifndef TYPE +#define TYPE _Float128 +#endif + +TYPE +return_convert_uchar_to_float128_mem (unsigned char *p_uc) +{ + return (TYPE) p_uc[10]; +} + +TYPE +return_convert_schar_to_float128_mem (signed char *p_sc) +{ + return (TYPE) p_sc[10]; +} + +TYPE +return_convert_ushort_to_float128_mem (unsigned short *p_us) +{ + return (TYPE) p_us[10]; +} + +TYPE +return_convert_sshort_to_float128_mem (short *p_ss) +{ + return (TYPE) p_ss[10]; +} + +/* { dg-final { scan-assembler {\mlxsi[bh]zx\M} } } */ +/* { dg-final { scan-assembler {\mvexts[bh]2d\M} } } */ +/* { dg-final { scan-assembler-not {\mextsb\M} } } */ +/* { dg-final { scan-assembler-not {\ml[bh][az]\M} } } */ +/* { dg-final { scan-assembler-not {\mmtvsrw[az]\M} } } */ + -- 2.30.2