From 3238ee7d354aed51eb61ce5a8c2799f56f2cb4b2 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 11:04:18 +0200
Subject: [PATCH] check muxes per type

---
 tests/anlogic/mux.v  | 35 -----------------------------------
 tests/anlogic/mux.ys | 44 +++++++++++++++++++++++++++++++++++++-------
 2 files changed, 37 insertions(+), 42 deletions(-)

diff --git a/tests/anlogic/mux.v b/tests/anlogic/mux.v
index 0814b733e..27bc0bf0b 100644
--- a/tests/anlogic/mux.v
+++ b/tests/anlogic/mux.v
@@ -63,38 +63,3 @@ module mux16 (D, S, Y);
 assign Y = D[S];
 
 endmodule
-
-
-module top (
-input [3:0] S,
-input [15:0] D,
-output M2,M4,M8,M16
-);
-
-mux2 u_mux2 (
-        .S (S[0]),
-        .A (D[0]),
-        .B (D[1]),
-        .Y (M2)
-    );
-
-
-mux4 u_mux4 (
-        .S (S[1:0]),
-        .D (D[3:0]),
-        .Y (M4)
-    );
-
-mux8 u_mux8 (
-        .S (S[2:0]),
-        .D (D[7:0]),
-        .Y (M8)
-    );
-
-mux16 u_mux16 (
-        .S (S[3:0]),
-        .D (D[15:0]),
-        .Y (M16)
-    );
-
-endmodule
diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys
index 84a8bcccf..354fc836c 100644
--- a/tests/anlogic/mux.ys
+++ b/tests/anlogic/mux.ys
@@ -1,12 +1,42 @@
 read_verilog mux.v
+design -save read
+
+proc
+hierarchy -top mux2
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT3
+
+select -assert-none t:AL_MAP_LUT3 %% t:* %D
+
+design -load read
+proc
+hierarchy -top mux4
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT6
+
+select -assert-none t:AL_MAP_LUT6 %% t:* %D
+
+design -load read
+proc
+hierarchy -top mux8
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 3 t:AL_MAP_LUT4
+select -assert-count 1 t:AL_MAP_LUT6
+
+select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D
+
+design -load read
 proc
-flatten
+hierarchy -top mux16
 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 5 t:AL_MAP_LUT6
 
-select -assert-count 1  t:AL_MAP_LUT3
-select -assert-count 4  t:AL_MAP_LUT4
-select -assert-count 4  t:AL_MAP_LUT5
-select -assert-count 1  t:AL_MAP_LUT6
-select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D
+select -assert-none t:AL_MAP_LUT6 %% t:* %D
-- 
2.30.2