From 324e009dd199361d5c84e6a15dca1b1be24a6b94 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Jun 2018 18:45:11 +0100
Subject: [PATCH] add ddr3 ohwr link

---
 shakti/m_class/DDR.mdwn | 1 +
 1 file changed, 1 insertion(+)

diff --git a/shakti/m_class/DDR.mdwn b/shakti/m_class/DDR.mdwn
index 8bae234cc..8607cddf1 100644
--- a/shakti/m_class/DDR.mdwn
+++ b/shakti/m_class/DDR.mdwn
@@ -1,3 +1,4 @@
 # DDR (DRAM) Controller and PHY
 
 * <https://github.com/enjoy-digital/litedram> - controller inc. DDR3 / LPDDR3
+* <https://www.ohwr.org/projects/ddr3-sp6-core/wiki/wiki> - CERN DDR3 ctrl
-- 
2.30.2