From 3260e33330a98a516d711365a6b5f64b3fe5e1b7 Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 19 May 2020 15:35:43 +0100 Subject: [PATCH] --- 3d_gpu/architecture/tomasulo_transformation.mdwn | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/3d_gpu/architecture/tomasulo_transformation.mdwn b/3d_gpu/architecture/tomasulo_transformation.mdwn index 60ff2e171..ae1700917 100644 --- a/3d_gpu/architecture/tomasulo_transformation.mdwn +++ b/3d_gpu/architecture/tomasulo_transformation.mdwn @@ -167,3 +167,17 @@ proper stratification and design of the register files, massive Vector parallelism at the pipelines would be kept fully occupied without an overwhelming increase in gates or power consumption that would normally be expected, and scalar performance would be similarly high as well. + +# Terminology notes + +These terms help understand that conceptually there is no difference +in the capabilities of Tomasulo and Scoreboards. + +| Tomasulo name | Scoreboard name | +| ----- | ---- | +| Reorder Buffer | hybrid of Shadow, FU-FU and FU-Regs Matrices | +| Reservation Station CAMs | each RS Row is "Computation Unit latches" | +| "register renaming" | "nameless" registers (Comp Unit latches) | +| part-ROB, part-RS | Q-Tables | +| blocking Common Data Bus | fan-out Read Reg, fan-in Write, OpFwd Bus(es)| +| Centralised regfile(s) | Centralised regfile(s) | -- 2.30.2