From 32800f06dda2eb1002936f758bdd645ce3d77eef Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 22 Sep 2022 13:11:48 +0100 Subject: [PATCH] --- openpower/sv/branches.mdwn | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index 5b634589a..6549a4f91 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -569,22 +569,35 @@ when and why CTR is decremented (CTRtest Mode) and whether LR is updated (which is unconditional in v3.0B when LK=1, and conditional in SVP64 when LRu=1). +Inline comments highlight the fact that the Scalar Branch behaviour +and pseudocode is still clearly visible and embedded within the +Vectorised variant: + ``` if (mode_is_64bit) then M <- 0 else M <- 32 +# the bit of CR to test, if the predicate bit is zero, +# is overridden testbit = CR[BI+32] if ¬predicate_bit then testbit = SVRMmode.SNZ +# otherwise apart from the override ctr_ok and cond_ok +# are exactly the same ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3]) cond_ok <- BO[0] | ¬(testbit ^ BO[1]) if ¬predicate_bit & ¬SVRMmode.sz then + # this is entirely new: CTR-test mode still decrements CTR + # even when predicate-bits are zero if ¬BO[2] & CTRtest & ¬CTi then CTR = CTR - 1 # instruction finishes here else + # usual BO[2] CTR-mode now under CTR-test mode as well if ¬BO[2] & ¬(CTRtest & (cond_ok ^ CTi)) then CTR <- CTR - 1 + # new VLset mode, conditional test truncates VL if VLSET and VSb = (cond_ok & ctr_ok) then if SVRMmode.VLI then SVSTATE.VL = srcstep+1 else SVSTATE.VL = srcstep + # usual LR is now conditional, but also joined by SVLR lr_ok <- LK svlr_ok <- SVRMmode.SL if ctr_ok & cond_ok then -- 2.30.2