From 32853b1f8d8cefff36bf5852a04cdaef1bcb2035 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 20 Feb 2019 16:30:30 -0800 Subject: [PATCH] lut/not/and suffix to be ${lut,not,and} --- frontends/aiger/aigerparse.cc | 26 +++++++++++++------------- passes/techmap/abc9.cc | 8 ++++---- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 426e88e53..28f91d6b9 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -163,12 +163,12 @@ void AigerReader::parse_aiger() RTLIL::Wire *wire = module->wire(name); if (wire) { - RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str())); + RTLIL::Cell* driver = module->cell(stringf("%s$lut", wire->name.c_str())); module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0))); if (driver) - module->rename(driver, stringf("%slut", wire->name.c_str())); + module->rename(driver, stringf("%s$lut", wire->name.c_str())); } // Do not make ports with a mix of input/output into @@ -246,7 +246,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera } log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str()); - module->addNotGate(stringf("\\__%d__not", variable), wire_inv, wire); // FIXME: is "not" the right suffix? + module->addNotGate(stringf("\\__%d__$not", variable), wire_inv, wire); // FIXME: is "$not" the right suffix? return wire; } @@ -325,10 +325,10 @@ void AigerReader::parse_xaiger() lut_mask[j] = o.as_const()[0]; ce.pop(); } - RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__and", rootNodeID)); + RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID)); log_assert(output_cell); module->remove(output_cell); - module->addLut(stringf("\\__%d__lut", rootNodeID), input_sig, output_sig, std::move(lut_mask)); + module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask)); } } else if (c == 'n') { @@ -353,8 +353,8 @@ void AigerReader::parse_xaiger() module->rename(wire, stringf("\\%s", s.c_str())); - RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str())); - module->rename(driver, stringf("%slut", wire->name.c_str())); + RTLIL::Cell* driver = module->cell(stringf("%s$lut", wire->name.c_str())); + module->rename(driver, stringf("%s$lut", wire->name.c_str())); std::getline(f, line); // Ignore up to start of next line ++line_count; @@ -391,7 +391,7 @@ void AigerReader::parse_xaiger() log_assert(wire); log_assert(wire->port_output); - RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str())); + RTLIL::Cell* driver = module->cell(stringf("%s$lut", wire->name.c_str())); if (index == 0) module->rename(wire, RTLIL::escape_id(symbol)); @@ -402,7 +402,7 @@ void AigerReader::parse_xaiger() } if (driver) - module->rename(driver, stringf("%slut", wire->name.c_str())); + module->rename(driver, stringf("%s$lut", wire->name.c_str())); } else log_error("Symbol type '%s' not recognised.\n", type.c_str()); @@ -415,12 +415,12 @@ void AigerReader::parse_xaiger() RTLIL::Wire *wire = module->wire(name); if (wire) { - RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str())); + RTLIL::Cell* driver = module->cell(stringf("%s$lut", wire->name.c_str())); module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0))); if (driver) - module->rename(driver, stringf("%slut", wire->name.c_str())); + module->rename(driver, stringf("%s$lut", wire->name.c_str())); } // Do not make ports with a mix of input/output into @@ -581,7 +581,7 @@ void AigerReader::parse_aiger_ascii() RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); - module->addAndGate(o_wire->name.str() + "and", i1_wire, i2_wire, o_wire); + module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire); } std::getline(f, line); } @@ -712,7 +712,7 @@ void AigerReader::parse_aiger_binary() RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); - module->addAndGate(o_wire->name.str() + "and", i1_wire, i2_wire, o_wire); + module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire); } } diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index cc906bae7..96f55d5d3 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -592,7 +592,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (a_bit.wire->port_input) { // If it's a NOT gate that comes from a primary input directly // then implement it using a LUT - cell = module->addLut(remap_name(stringf("%slut", c->name.c_str())), + cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())), RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset), RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset), 1); @@ -603,9 +603,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // (TODO: Optimise by not cloning unless will increase depth) RTLIL::IdString driver_name; if (GetSize(a_bit.wire) == 1) - driver_name = stringf("%slut", a_bit.wire->name.c_str()); + driver_name = stringf("%s$lut", a_bit.wire->name.c_str()); else - driver_name = stringf("%s[%d]lut", a_bit.wire->name.c_str(), a_bit.offset); + driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset); RTLIL::Cell* driver = mapped_mod->cell(driver_name); log_assert(driver); auto driver_a = driver->getPort("\\A").chunks(); @@ -616,7 +616,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (b == RTLIL::State::S0) b = RTLIL::State::S1; else if (b == RTLIL::State::S1) b = RTLIL::State::S0; } - cell = module->addLut(remap_name(stringf("%slut", c->name.c_str())), + cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())), driver_a, RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset), driver_lut); -- 2.30.2