From 3293926413f84c4db4747537bf05c42a4c523c55 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 22 Aug 2020 23:33:10 -0700 Subject: [PATCH] sim: Create a Workload object for SE mode. The workload object is still optional for the sake of compatibility, even though it probably shouldn't be in the long term. If a simulation is just a collection of components with nothing in particular running on it, for instance driven by a traffic generator, should it even have a System object in the first place? Change-Id: I8bcda72bdfa3730248226fb62f0bba9a83243d95 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33278 Reviewed-by: Matthew Poremba Maintainer: Gabe Black Tested-by: kokoro --- configs/dram/low_power_sweep.py | 2 + configs/example/apu_se.py | 3 +- configs/example/arm/starter_se.py | 2 + configs/example/hmc_hello.py | 1 + configs/example/se.py | 2 +- configs/learning_gem5/part1/simple.py | 2 + configs/learning_gem5/part1/two_level.py | 2 + configs/learning_gem5/part2/simple_cache.py | 2 + configs/learning_gem5/part2/simple_memobj.py | 2 + configs/learning_gem5/part3/simple_ruby.py | 2 + configs/splash2/cluster.py | 2 + configs/splash2/run.py | 3 +- src/sim/SConscript | 1 + src/sim/System.py | 2 +- src/sim/Workload.py | 4 + src/sim/se_workload.cc | 40 +++++++++ src/sim/se_workload.hh | 81 +++++++++++++++++++ tests/configs/gpu-ruby.py | 3 +- tests/gem5/cpu_tests/run.py | 2 + .../m5threads_test_atomic/atomic_system.py | 2 + 20 files changed, 155 insertions(+), 5 deletions(-) create mode 100644 src/sim/se_workload.cc create mode 100644 src/sim/se_workload.hh diff --git a/configs/dram/low_power_sweep.py b/configs/dram/low_power_sweep.py index 292b0fa73..a9f7057b0 100644 --- a/configs/dram/low_power_sweep.py +++ b/configs/dram/low_power_sweep.py @@ -93,6 +93,8 @@ system.clk_domain = SrcClockDomain(clock = '2.0GHz', voltage_domain = VoltageDomain(voltage = '1V')) +system.workload = SEWorkload() + # We are fine with 256 MB memory for now. mem_range = AddrRange('256MB') # Start address is 0 diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py index 03418c328..077ce4c77 100644 --- a/configs/example/apu_se.py +++ b/configs/example/apu_se.py @@ -500,7 +500,8 @@ cpu_list = cpu_list + [shader] + cp_list system = System(cpu = cpu_list, mem_ranges = [AddrRange(options.mem_size)], cache_line_size = options.cacheline_size, - mem_mode = mem_mode) + mem_mode = mem_mode, + workload = SEWorkload()) if fast_forward: system.future_cpu = future_cpu_list system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) diff --git a/configs/example/arm/starter_se.py b/configs/example/arm/starter_se.py index 0003ce994..d342420b5 100644 --- a/configs/example/arm/starter_se.py +++ b/configs/example/arm/starter_se.py @@ -171,6 +171,8 @@ def create(args): (len(processes), args.num_cores)) sys.exit(1) + system.workload = SEWorkload() + # Assign one workload to each CPU for cpu, workload in zip(system.cpu_cluster.cpus, processes): cpu.workload = workload diff --git a/configs/example/hmc_hello.py b/configs/example/hmc_hello.py index a68251981..706fc2b68 100644 --- a/configs/example/hmc_hello.py +++ b/configs/example/hmc_hello.py @@ -50,6 +50,7 @@ HMC.add_options(parser) options = parser.parse_args() # create the system we are going to simulate system = System() +system.workload = SEWorkload() # use timing mode for the interaction between master-slave ports system.mem_mode = 'timing' # set the clock fequency of the system diff --git a/configs/example/se.py b/configs/example/se.py index 200a0dee5..f3fea61bd 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -173,7 +173,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)], mem_mode = test_mem_mode, mem_ranges = [AddrRange(options.mem_size)], cache_line_size = options.cacheline_size, - workload = NULL) + workload = SEWorkload()) if numThreads > 1: system.multi_thread = True diff --git a/configs/learning_gem5/part1/simple.py b/configs/learning_gem5/part1/simple.py index 22b2cf7b4..cb785b6e7 100644 --- a/configs/learning_gem5/part1/simple.py +++ b/configs/learning_gem5/part1/simple.py @@ -94,6 +94,8 @@ thispath = os.path.dirname(os.path.realpath(__file__)) binary = os.path.join(thispath, '../../../', 'tests/test-progs/hello/bin/', isa, 'linux/hello') +system.workload = SEWorkload() + # Create a process for a simple "Hello World" application process = Process() # Set the command diff --git a/configs/learning_gem5/part1/two_level.py b/configs/learning_gem5/part1/two_level.py index 53e11378b..50d1d5f9e 100644 --- a/configs/learning_gem5/part1/two_level.py +++ b/configs/learning_gem5/part1/two_level.py @@ -137,6 +137,8 @@ system.mem_ctrl.dram = DDR3_1600_8x8() system.mem_ctrl.dram.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master +system.workload = SEWorkload() + # Create a process for a simple "Hello World" application process = Process() # Set the command diff --git a/configs/learning_gem5/part2/simple_cache.py b/configs/learning_gem5/part2/simple_cache.py index 533aa23ad..391de8ba7 100644 --- a/configs/learning_gem5/part2/simple_cache.py +++ b/configs/learning_gem5/part2/simple_cache.py @@ -84,6 +84,8 @@ system.mem_ctrl.port = system.membus.master # Connect the system up to the membus system.system_port = system.membus.slave +system.workload = SEWorkload() + # Create a process for a simple "Hello World" application process = Process() # Set the command diff --git a/configs/learning_gem5/part2/simple_memobj.py b/configs/learning_gem5/part2/simple_memobj.py index b7d256189..80f660221 100644 --- a/configs/learning_gem5/part2/simple_memobj.py +++ b/configs/learning_gem5/part2/simple_memobj.py @@ -82,6 +82,8 @@ system.mem_ctrl.port = system.membus.master # Connect the system up to the membus system.system_port = system.membus.slave +system.workload = SEWorkload() + # Create a process for a simple "Hello World" application process = Process() # Set the command diff --git a/configs/learning_gem5/part3/simple_ruby.py b/configs/learning_gem5/part3/simple_ruby.py index 760a16892..f0a9e08c2 100644 --- a/configs/learning_gem5/part3/simple_ruby.py +++ b/configs/learning_gem5/part3/simple_ruby.py @@ -89,6 +89,8 @@ thispath = os.path.dirname(os.path.realpath(__file__)) binary = os.path.join(thispath, '../../../', 'tests/test-progs/threads/bin/', isa, 'linux/threads') +system.workload = SEWorkload() + # Create a process for a simple "multi-threaded" application process = Process() # Set the command diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py index 0e92625ce..2b36c825d 100644 --- a/configs/splash2/cluster.py +++ b/configs/splash2/cluster.py @@ -216,6 +216,8 @@ system.clock = '1GHz' system.toL2bus = L2XBar(clock = busFrequency) system.l2 = L2(size = options.l2size, assoc = 8) +system.workload = SEWorkload() + # ---------------------- # Connect the L2 cache and memory together # ---------------------- diff --git a/configs/splash2/run.py b/configs/splash2/run.py index 7ad2dac2a..b3b878703 100644 --- a/configs/splash2/run.py +++ b/configs/splash2/run.py @@ -195,7 +195,8 @@ else: # Create a system, and add system wide objects # ---------------------- system = System(cpu = cpus, physmem = SimpleMemory(), - membus = SystemXBar(clock = busFrequency)) + membus = SystemXBar(clock = busFrequency), + workload = SEWorkload()) system.clock = '1GHz' system.toL2bus = L2XBar(clock = busFrequency) diff --git a/src/sim/SConscript b/src/sim/SConscript index 0bdf921f4..6bda82859 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -63,6 +63,7 @@ Source('redirect_path.cc') Source('root.cc') Source('serialize.cc') Source('drain.cc') +Source('se_workload.cc') Source('sim_events.cc') Source('sim_object.cc') Source('sub_system.cc') diff --git a/src/sim/System.py b/src/sim/System.py index caf32fb56..a2f605604 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -111,7 +111,7 @@ class System(SimObject): work_cpus_ckpt_count = Param.Counter(0, "create checkpoint when active cpu count value is reached") - workload = Param.Workload(NULL, "Operating system kernel") + workload = Param.Workload(NULL, "Workload to run on this system") init_param = Param.UInt64(0, "numerical value to pass into simulator") readfile = Param.String("", "file to read startup script from") symbolfile = Param.String("", "file to get the symbols from") diff --git a/src/sim/Workload.py b/src/sim/Workload.py index 1e35abec1..f1974bbe9 100644 --- a/src/sim/Workload.py +++ b/src/sim/Workload.py @@ -50,3 +50,7 @@ class KernelWorkload(Workload): load_addr_offset = Param.UInt64(0, "Address to offset the kernel with") command_line = Param.String("a", "boot flags to pass to the kernel") + +class SEWorkload(Workload): + type = 'SEWorkload' + cxx_header = "sim/se_workload.hh" diff --git a/src/sim/se_workload.cc b/src/sim/se_workload.cc new file mode 100644 index 000000000..f2a01d53a --- /dev/null +++ b/src/sim/se_workload.cc @@ -0,0 +1,40 @@ +/* + * Copyright 2020 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "sim/se_workload.hh" + +#include "params/SEWorkload.hh" + +SEWorkload::SEWorkload(const Params &p) : Workload(&p), _params(p) +{ +} + +SEWorkload * +SEWorkloadParams::create() +{ + return new SEWorkload(*this); +} diff --git a/src/sim/se_workload.hh b/src/sim/se_workload.hh new file mode 100644 index 000000000..b72e8240d --- /dev/null +++ b/src/sim/se_workload.hh @@ -0,0 +1,81 @@ +/* + * Copyright 2020 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SIM_SE_WORKLOAD_HH__ +#define __SIM_SE_WORKLOAD_HH__ + +#include "params/SEWorkload.hh" +#include "sim/workload.hh" + +class SEWorkload : public Workload +{ + public: + using Params = SEWorkloadParams; + + protected: + const Params &_params; + + public: + const Params ¶ms() const { return _params; } + + SEWorkload(const Params &p); + + Addr + getEntry() const override + { + // This object represents the OS, not the individual processes running + // within it. + panic("No workload entry point for syscall emulation mode."); + } + + Loader::Arch + getArch() const override + { + // ISA specific subclasses should implement this method. + // This implemenetation is just to avoid having to implement those for + // now, and will be removed in the future. + panic("SEWorkload::getArch() not implemented."); + } + + const Loader::SymbolTable & + symtab(ThreadContext *) override + { + // This object represents the OS, not the individual processes running + // within it. + panic("No workload symbol table for syscall emulation mode."); + } + + bool + insertSymbol(const Loader::Symbol &symbol) override + { + // This object represents the OS, not the individual processes running + // within it. + panic("No workload symbol table for syscall emulation mode."); + } +}; + +#endif // __SIM_SE_WORKLOAD_HH__ diff --git a/tests/configs/gpu-ruby.py b/tests/configs/gpu-ruby.py index 155775a0b..a463fe3b4 100644 --- a/tests/configs/gpu-ruby.py +++ b/tests/configs/gpu-ruby.py @@ -261,7 +261,8 @@ cpu_list = [cpu] + [shader] + [dispatcher] system = System(cpu = cpu_list, mem_ranges = [AddrRange(options.mem_size)], - mem_mode = 'timing') + mem_mode = 'timing', + workload = SEWorkload()) # Dummy voltage domain for all our clock domains system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) diff --git a/tests/gem5/cpu_tests/run.py b/tests/gem5/cpu_tests/run.py index 4d2daf136..b893b80ad 100644 --- a/tests/gem5/cpu_tests/run.py +++ b/tests/gem5/cpu_tests/run.py @@ -119,6 +119,8 @@ args = parser.parse_args() system = System() +system.workload = SEWorkload() + system.clk_domain = SrcClockDomain() system.clk_domain.clock = '1GHz' system.clk_domain.voltage_domain = VoltageDomain() diff --git a/tests/gem5/m5threads_test_atomic/atomic_system.py b/tests/gem5/m5threads_test_atomic/atomic_system.py index 2d9b12937..a08be5c5f 100644 --- a/tests/gem5/m5threads_test_atomic/atomic_system.py +++ b/tests/gem5/m5threads_test_atomic/atomic_system.py @@ -40,6 +40,8 @@ args = parser.parse_args() root = Root(full_system = False) root.system = System() +root.system.workload = SEWorkload() + root.system.clk_domain = SrcClockDomain() root.system.clk_domain.clock = '3GHz' root.system.clk_domain.voltage_domain = VoltageDomain() -- 2.30.2