From 32940bf81eb25739d945c85a50f2152daddfcf5d Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 12 Apr 2022 04:09:53 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index f224e0902..942158bc1 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -71,11 +71,10 @@ SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations: | 4 | 5 | 19-20 | 21 | 22 23 | description | | - | - | ----- | --- |---------|----------------- | -|sz |SNZ| 0 0 | 0 | dz / | normal mode | -|sz |SNZ| 0 0 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 | -|sz |SNZ| 0 0 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 | -|sz |SNZ| 0 0 | 1 | SVM RG | subvector reduce mode, SUBVL>1 | -|sz |SNZ| 0 1 | rsv | rsvd | reserved | +|sz |SNZ| 0 RG | 0 | dz / | normal mode | +|sz |SNZ| 0 RG | 1 | 0 / | scalar reduce mode (mapreduce), SUBVL=1 | +|sz |SNZ| 0 RG | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 | +|sz |SNZ| 0 RG | 1 | SVM / | subvector reduce mode, SUBVL>1 | |sz |SNZ| 1 VLI | inv | CR-bit | Ffirst 3-bit mode | |sz |SNZ| 1 VLI | inv | dz / | Ffirst 5-bit mode | -- 2.30.2