From 329ad8c8fd96bf86f7939d189407a381c7b9b91d Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 7 Oct 2022 17:34:41 -0700 Subject: [PATCH] add equality constraints --- src/bigint_presentation_code/toom_cook.py | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/bigint_presentation_code/toom_cook.py b/src/bigint_presentation_code/toom_cook.py index 58c9a44..2209d8b 100644 --- a/src/bigint_presentation_code/toom_cook.py +++ b/src/bigint_presentation_code/toom_cook.py @@ -273,6 +273,17 @@ class VecArg: yield GPR(r[index]) +@final +@plain_data(unsafe_hash=True, frozen=True) +class EqualityConstraint: + __slots__ = "lhs", "rhs" + + def __init__(self, lhs, rhs): + # type: (SSAVal, SSAVal) -> None + self.lhs = lhs + self.rhs = rhs + + @plain_data(unsafe_hash=True, frozen=True) class Op(metaclass=ABCMeta): __slots__ = () @@ -308,6 +319,11 @@ class Op(metaclass=ABCMeta): # type: (SSAVal, dict[SSAVal, PhysLoc]) -> Iterable[PhysLoc] ... + def get_equality_constraints(self): + # type: () -> Iterable[EqualityConstraint] + if False: + yield ... + def __init__(self): pass @@ -426,6 +442,10 @@ class OpAddSubE(Op): else: yield from self.RB.possible_reg_assignments(val, value_assignments) + def get_equality_constraints(self): + # type: () -> Iterable[EqualityConstraint] + yield EqualityConstraint(self.CY_in, self.CY_out) + def to_reg_set(v): # type: (None | GPR | range) -> set[GPR] @@ -500,6 +520,10 @@ class OpBigIntMulDiv(Op): val, value_assignments, conflicting_regs=to_reg_set(RT_range) | to_reg_set(RC_RS_reg)) + def get_equality_constraints(self): + # type: () -> Iterable[EqualityConstraint] + yield EqualityConstraint(self.RC, self.RS) + @final @unique @@ -715,6 +739,10 @@ class OpStore(Op): else: yield from self.RS.possible_reg_assignments(value_assignments) + def get_equality_constraints(self): + # type: () -> Iterable[EqualityConstraint] + yield EqualityConstraint(self.mem_in, self.mem_out) + @plain_data(unsafe_hash=True, frozen=True) @final -- 2.30.2