From 32a046ab0d7717256f16f59d87438474e825fcb8 Mon Sep 17 00:00:00 2001 From: Tom Tromey Date: Thu, 8 Apr 2021 08:52:50 -0600 Subject: [PATCH] Add system includes in sim This updates various parts of the sim to include missing system headers. I made the includes unconditional, because other parts of the tree are already doing this. 2021-04-08 Tom Tromey * traps.c: Include stdlib.h. * cris-tmpl.c: Include stdlib.h. sim/erc32/ChangeLog 2021-04-08 Tom Tromey * func.c: Include sys/time.h. sim/frv/ChangeLog 2021-04-08 Tom Tromey * traps.c: Include stdlib.h. * registers.c: Include stdlib.h. * profile.c: Include stdlib.h. * memory.c: Include stdlib.h. * interrupts.c: Include stdlib.h. * frv.c: Include stdlib.h. * cache.c: Include stdlib.h. sim/iq2000/ChangeLog 2021-04-08 Tom Tromey * iq2000.c: Include stdlib.h. sim/m32r/ChangeLog 2021-04-08 Tom Tromey * traps.c: Include stdlib.h. * m32r.c: Include stdlib.h. sim/ppc/ChangeLog 2021-04-08 Tom Tromey * emul_unix.c: Include time.h. --- sim/cris/ChangeLog | 5 +++++ sim/cris/cris-tmpl.c | 2 ++ sim/cris/traps.c | 1 + sim/erc32/ChangeLog | 4 ++++ sim/erc32/func.c | 1 + sim/frv/ChangeLog | 10 ++++++++++ sim/frv/cache.c | 1 + sim/frv/frv.c | 1 + sim/frv/interrupts.c | 1 + sim/frv/memory.c | 1 + sim/frv/profile.c | 1 + sim/frv/registers.c | 1 + sim/frv/traps.c | 2 ++ sim/iq2000/ChangeLog | 4 ++++ sim/iq2000/iq2000.c | 1 + sim/m32r/ChangeLog | 5 +++++ sim/m32r/m32r.c | 1 + sim/m32r/traps.c | 1 + sim/ppc/ChangeLog | 4 ++++ sim/ppc/emul_unix.c | 1 + 20 files changed, 48 insertions(+) diff --git a/sim/cris/ChangeLog b/sim/cris/ChangeLog index 3899045c7bf..45907986303 100644 --- a/sim/cris/ChangeLog +++ b/sim/cris/ChangeLog @@ -1,3 +1,8 @@ +2021-04-08 Tom Tromey + + * traps.c: Include stdlib.h. + * cris-tmpl.c: Include stdlib.h. + 2021-04-02 Mike Frysinger * aclocal.m4, configure: Regenerate. diff --git a/sim/cris/cris-tmpl.c b/sim/cris/cris-tmpl.c index b5ad7189191..95579dbffa9 100644 --- a/sim/cris/cris-tmpl.c +++ b/sim/cris/cris-tmpl.c @@ -25,6 +25,8 @@ along with this program. If not, see . */ #include "cgen-mem.h" #include "cgen-ops.h" +#include + #define MY(f) XCONCAT3(crisv,BASENUM,f) /* Dispatcher for break insn. */ diff --git a/sim/cris/traps.c b/sim/cris/traps.c index 2aaa1f43b16..1c8ca41d14e 100644 --- a/sim/cris/traps.c +++ b/sim/cris/traps.c @@ -23,6 +23,7 @@ along with this program. If not, see . */ #include "bfd.h" /* FIXME: get rid of targ-vals.h usage everywhere else. */ +#include #include #include #ifdef HAVE_UNISTD_H diff --git a/sim/erc32/ChangeLog b/sim/erc32/ChangeLog index 72de217ece9..3b85c66beeb 100644 --- a/sim/erc32/ChangeLog +++ b/sim/erc32/ChangeLog @@ -1,3 +1,7 @@ +2021-04-08 Tom Tromey + + * func.c: Include sys/time.h. + 2021-04-08 Tom Tromey * sis.c (run_sim, main): Use new-style declaration. diff --git a/sim/erc32/func.c b/sim/erc32/func.c index 98217f062ae..c6dfa1927ad 100644 --- a/sim/erc32/func.c +++ b/sim/erc32/func.c @@ -26,6 +26,7 @@ #include #include "sim-config.h" #include +#include #define VAL(x) strtoul(x,(char **)NULL,0) diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog index c32d2c5131c..a067ff80c3e 100644 --- a/sim/frv/ChangeLog +++ b/sim/frv/ChangeLog @@ -1,3 +1,13 @@ +2021-04-08 Tom Tromey + + * traps.c: Include stdlib.h. + * registers.c: Include stdlib.h. + * profile.c: Include stdlib.h. + * memory.c: Include stdlib.h. + * interrupts.c: Include stdlib.h. + * frv.c: Include stdlib.h. + * cache.c: Include stdlib.h. + 2021-04-08 Tom Tromey * sim-if.c (sim_open, frv_sim_close, sim_create_inferior): Use diff --git a/sim/frv/cache.c b/sim/frv/cache.c index 9e2a99f5f7e..c10d46373f5 100644 --- a/sim/frv/cache.c +++ b/sim/frv/cache.c @@ -24,6 +24,7 @@ along with this program. If not, see . */ #include "sim-main.h" #include "cache.h" #include "bfd.h" +#include void frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache) diff --git a/sim/frv/frv.c b/sim/frv/frv.c index 88290be3e8e..fee59c2aae7 100644 --- a/sim/frv/frv.c +++ b/sim/frv/frv.c @@ -28,6 +28,7 @@ along with this program. If not, see . */ #include "bfd.h" #include "gdb/sim-frv.h" #include +#include /* Maintain a flag in order to know when to write the address of the next VLIW instruction into the LR register. Used by JMPL. JMPIL, and CALL diff --git a/sim/frv/interrupts.c b/sim/frv/interrupts.c index d38620c9a72..0b8ed763987 100644 --- a/sim/frv/interrupts.c +++ b/sim/frv/interrupts.c @@ -22,6 +22,7 @@ along with this program. If not, see . */ #include "sim-main.h" #include "bfd.h" +#include /* FR-V Interrupt table. Describes the interrupts supported by the FR-V. diff --git a/sim/frv/memory.c b/sim/frv/memory.c index ea7f68e4349..5978d151627 100644 --- a/sim/frv/memory.c +++ b/sim/frv/memory.c @@ -23,6 +23,7 @@ along with this program. If not, see . */ #include "sim-main.h" #include "cgen-mem.h" #include "bfd.h" +#include /* Check for alignment and access restrictions. Return the corrected address. */ diff --git a/sim/frv/profile.c b/sim/frv/profile.c index c08950886d1..441590eb581 100644 --- a/sim/frv/profile.c +++ b/sim/frv/profile.c @@ -24,6 +24,7 @@ along with this program. If not, see . #include "sim-main.h" #include "bfd.h" +#include #if WITH_PROFILE_MODEL_P diff --git a/sim/frv/registers.c b/sim/frv/registers.c index c9d26fda018..764a6755b3f 100644 --- a/sim/frv/registers.c +++ b/sim/frv/registers.c @@ -22,6 +22,7 @@ along with this program. If not, see . */ #include "sim-main.h" #include "bfd.h" +#include #define IMPL 1 /* Implemented */ #define SUP 1 /* Supervisor register */ diff --git a/sim/frv/traps.c b/sim/frv/traps.c index 79ea1571ac2..c0ed9b1c49f 100644 --- a/sim/frv/traps.c +++ b/sim/frv/traps.c @@ -29,6 +29,8 @@ along with this program. If not, see . */ #include "bfd.h" #include "libiberty.h" +#include + CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot; /* The semantic code invokes this for invalid (unrecognized) instructions. */ diff --git a/sim/iq2000/ChangeLog b/sim/iq2000/ChangeLog index 970df7988a0..95ad2a8ce6e 100644 --- a/sim/iq2000/ChangeLog +++ b/sim/iq2000/ChangeLog @@ -1,3 +1,7 @@ +2021-04-08 Tom Tromey + + * iq2000.c: Include stdlib.h. + 2021-04-08 Tom Tromey * sim-if.c (sim_open, sim_create_inferior): Use new-style diff --git a/sim/iq2000/iq2000.c b/sim/iq2000/iq2000.c index 23a342983ce..e03c47919fd 100644 --- a/sim/iq2000/iq2000.c +++ b/sim/iq2000/iq2000.c @@ -23,6 +23,7 @@ #include "sim-main.h" #include "cgen-mem.h" #include "cgen-ops.h" +#include enum { diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog index f964397d5a3..3252bdea457 100644 --- a/sim/m32r/ChangeLog +++ b/sim/m32r/ChangeLog @@ -1,3 +1,8 @@ +2021-04-08 Tom Tromey + + * traps.c: Include stdlib.h. + * m32r.c: Include stdlib.h. + 2021-04-08 Tom Tromey * sim-if.c (sim_open, sim_create_inferior): Use new-style diff --git a/sim/m32r/m32r.c b/sim/m32r/m32r.c index 1c5379cfd74..1d0a7356bb0 100644 --- a/sim/m32r/m32r.c +++ b/sim/m32r/m32r.c @@ -23,6 +23,7 @@ #include "sim-main.h" #include "cgen-mem.h" #include "cgen-ops.h" +#include /* Return the size of REGNO in bytes. */ diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c index 9edf66b58f1..9fca2b1ec1d 100644 --- a/sim/m32r/traps.c +++ b/sim/m32r/traps.c @@ -20,6 +20,7 @@ #include "sim-main.h" #include "sim-syscall.h" #include "targ-vals.h" +#include #define TRAP_FLUSH_CACHE 12 /* The semantic code invokes this for invalid (unrecognized) instructions. */ diff --git a/sim/ppc/ChangeLog b/sim/ppc/ChangeLog index 910996fe346..269411e2ab1 100644 --- a/sim/ppc/ChangeLog +++ b/sim/ppc/ChangeLog @@ -1,3 +1,7 @@ +2021-04-08 Tom Tromey + + * emul_unix.c: Include time.h. + 2021-04-08 Simon Marchi * Makefile.in: Set ASAN_OPTIONS when running igen. diff --git a/sim/ppc/emul_unix.c b/sim/ppc/emul_unix.c index 92c3c1ededf..2616ae408ba 100644 --- a/sim/ppc/emul_unix.c +++ b/sim/ppc/emul_unix.c @@ -124,6 +124,7 @@ int getrusage(); #endif #include +#include #if defined(BSD) && !defined(errno) && (BSD < 199306) /* here BSD as just a bug */ extern int errno; -- 2.30.2