From 32a1736cbeb8c9ffad0728b6c1011fb63954ecd1 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 7 Jan 2021 15:42:18 +0000 Subject: [PATCH] --- openpower/sv/setvl.mdwn | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index b40aa46e4..cb8524139 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -9,6 +9,22 @@ See links: Use of setvl results in changes to the MVL, VL and STATE SPRs. see [[sv/sprs]]♧ +# Behaviour and Rationale + +SV's Vector Engine is based on Cray-style Variable-length Vectorisation, +just like RVV. However unlike RVV, SV sits on top of the standard Scalar +regfiles: there is no separate Vector register numbering. Therefore, also +unlike RVV, SV does not have hard-coded "Lanes". The relevant parameter +in RVV is "MAXVL" and this is architecturally hard-coded into RVV systems, +anywhere from 1 to tens of thousands of Lanes in supercomputers. + +SV is more like how MMX used to sit on top of the x86 FP regfile. Therefore +when Vector operations are performed, the question has to be asked, "well, +how much of the regfile do you want to allocate to this operation?" and +the answer to that effectively needs to be parameterised. Hence: MAXVL +(MVL) is set from an immediate, so that the compiler may decide, statically, a guaranteed resource allocation. + + # Format *(Allocation of opcode TBD pending OPF ISA WG approval)* -- 2.30.2