From 32aa5e6d9416532ce2ccd52b3b100fb349aedbaa Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 18 Jun 2022 14:39:55 +0100
Subject: [PATCH]

---
 openpower/sv.mdwn | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 8d144e510..bb333141f 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -91,8 +91,6 @@ Pages being developed and examples
   contains explanations and further details
 * [[sv/svp64_quirks]] things in SVP64  that slightly break the rules
 * [[opcode_regs_deduped]] autogenerated table of SVP64 decoder augmentation
-* [[sv/vector_comparative_analysis]] - a list of Packed SIMD, GPU,
-  and other Scalable Vector ISAs
 * [[sv/sprs]] SPRs
 * SVP64 "Modes":
   - For condition register operations see [[sv/cr_ops]] - SVP64 Condition
@@ -173,9 +171,10 @@ Examples experiments future ideas discussion:
 Additional links:
 
 * <https://www.sigarch.org/simd-instructions-considered-harmful/>
+* [[sv/vector_isa_comparison]] - a list of Packed SIMD, GPU,
+  and other Scalable Vector ISAs
 * [[simple_v_extension]] old (deprecated) version
 * [[openpower/sv/llvm]]
-* [[openpower/sv/effect-of-more-decode-stages-on-reg-renaming]]
 
 # Major opcodes summary
 
-- 
2.30.2