From 32b84ef4ca50998914184fc4600d8e43674a9a22 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Sat, 4 Sep 2010 20:54:52 -0700 Subject: [PATCH] i965: Make pixel_xy results UW. There is a restriction on the destination of an operation involving a vector immediate being 128-bit aligned and the destination horizontal stride being equivalent to 2 bytes. Fixes bad pixel_x results from gl_FragCoord, where each pair had the same value. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 811d1082284..25a20e76042 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1211,6 +1211,8 @@ fs_visitor::emit_interpolation() this->current_annotation = "compute pixel centers"; this->pixel_x = fs_reg(this, glsl_type::uint_type); this->pixel_y = fs_reg(this, glsl_type::uint_type); + this->pixel_x.type = BRW_REGISTER_TYPE_UW; + this->pixel_y.type = BRW_REGISTER_TYPE_UW; emit(fs_inst(BRW_OPCODE_ADD, this->pixel_x, fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), -- 2.30.2