From 32c478af16e0186975b056a69d0bbd59b36a78bc Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 13 May 2013 15:45:06 +0200 Subject: [PATCH] top: integrate ADC for pots --- milkymist/{adc => counteradc}/__init__.py | 0 top.py | 6 +++++- 2 files changed, 5 insertions(+), 1 deletion(-) rename milkymist/{adc => counteradc}/__init__.py (100%) diff --git a/milkymist/adc/__init__.py b/milkymist/counteradc/__init__.py similarity index 100% rename from milkymist/adc/__init__.py rename to milkymist/counteradc/__init__.py diff --git a/top.py b/top.py index 029a02fd..4b8c4b87 100644 --- a/top.py +++ b/top.py @@ -8,7 +8,7 @@ from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi from migen.bank import csrgen from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \ - identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler + identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler, counteradc from cif import get_macros version = get_macros("common/version.h")["VERSION"][1:-1] @@ -77,6 +77,7 @@ class SoC(Module): "dvisampler0_edid_mem": 9, "dvisampler1": 10, "dvisampler1_edid_mem": 11, + "pots": 12, } interrupt_map = { @@ -148,6 +149,9 @@ class SoC(Module): self.submodules.asmiprobe = asmiprobe.ASMIprobe(self.asmicon.hub) self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), asmiport_dvi0) self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), asmiport_dvi1) + pots_pads = platform.request("dvi_pots") + self.submodules.pots = counteradc.CounterADC(pots_pads.charge, + [pots_pads.blackout, pots_pads.crossfade]) self.submodules.csrbankarray = csrgen.BankArray(self, lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override]) -- 2.30.2