From 32cac6f1ae656a45a32dbc3de0d8362c4b9703ca Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 27 Oct 2011 21:52:06 +0200 Subject: [PATCH] i386.c (ix86_print_operand): Handle 'q' and 'x' overrides for -masm=intel memory. * config/i386/i386.c (ix86_print_operand): Handle 'q' and 'x' overrides for -masm=intel memory. * config/i386/sse.md (sse2_cvtdq2pd, sse2_cvtps2pd, sse4_1_v8qiv8hi2, avx2_v8qiv8si2, sse4_1_v4hiv4si2, avx2_v4hiv4di2, sse4_1_v2siv2di2): Use %q1 instead of %1 for -masm=intel. (sse4_1_v4qiv4si2, avx2_v4qiv4di2, sse4_1_v2hiv2di2): Use %k1 instead of %1 for -masm=intel. (sse4_1_v2qiv2di2): Use %w1 instead of %1 for -masm=intel. From-SVN: r180579 --- gcc/ChangeLog | 12 ++++++++++++ gcc/config/i386/i386.c | 7 ++++++- gcc/config/i386/sse.md | 22 +++++++++++----------- 3 files changed, 29 insertions(+), 12 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 66d62cceb69..e64511d7eb0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2011-10-27 Jakub Jelinek + + * config/i386/i386.c (ix86_print_operand): Handle 'q' and 'x' + overrides for -masm=intel memory. + * config/i386/sse.md (sse2_cvtdq2pd, sse2_cvtps2pd, + sse4_1_v8qiv8hi2, avx2_v8qiv8si2, + sse4_1_v4hiv4si2, avx2_v4hiv4di2, + sse4_1_v2siv2di2): Use %q1 instead of %1 for -masm=intel. + (sse4_1_v4qiv4si2, avx2_v4qiv4di2, + sse4_1_v2hiv2di2): Use %k1 instead of %1 for -masm=intel. + (sse4_1_v2qiv2di2): Use %w1 instead of %1 for -masm=intel. + 2011-10-27 Martin Jambor * ipa-prop.c (compute_pass_through_member_ptrs): Rename parm_info diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index c6e09aecccf..7072d4264ef 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -14118,13 +14118,18 @@ ix86_print_operand (FILE *file, rtx x, int code) gcc_unreachable (); } - /* Check for explicit size override (codes 'b', 'w' and 'k') */ + /* Check for explicit size override (codes 'b', 'w', 'k', + 'q' and 'x') */ if (code == 'b') size = "BYTE"; else if (code == 'w') size = "WORD"; else if (code == 'k') size = "DWORD"; + else if (code == 'q') + size = "QWORD"; + else if (code == 'x') + size = "XMMWORD"; fputs (size, file); fputs (" PTR ", file); diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index c4366ba4ba0..25854e4ca7b 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -2529,7 +2529,7 @@ (match_operand:V4SI 1 "nonimmediate_operand" "xm") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2" - "%vcvtdq2pd\t{%1, %0|%0, %1}" + "%vcvtdq2pd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "maybe_vex") (set_attr "mode" "V2DF")]) @@ -2724,7 +2724,7 @@ (match_operand:V4SF 1 "nonimmediate_operand" "xm") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2" - "%vcvtps2pd\t{%1, %0|%0, %1}" + "%vcvtps2pd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssecvt") (set_attr "amdfam10_decode" "direct") (set_attr "athlon_decode" "double") @@ -9675,7 +9675,7 @@ (const_int 6) (const_int 7)]))))] "TARGET_SSE4_1" - "%vpmovbw\t{%1, %0|%0, %1}" + "%vpmovbw\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") @@ -9695,7 +9695,7 @@ (const_int 6) (const_int 7)]))))] "TARGET_AVX2" - "vpmovbd\t{%1, %0|%0, %1}" + "vpmovbd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") @@ -9711,7 +9711,7 @@ (const_int 2) (const_int 3)]))))] "TARGET_SSE4_1" - "%vpmovbd\t{%1, %0|%0, %1}" + "%vpmovbd\t{%1, %0|%0, %k1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") @@ -9738,7 +9738,7 @@ (const_int 2) (const_int 3)]))))] "TARGET_SSE4_1" - "%vpmovwd\t{%1, %0|%0, %1}" + "%vpmovwd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") @@ -9754,7 +9754,7 @@ (const_int 2) (const_int 3)]))))] "TARGET_AVX2" - "vpmovbq\t{%1, %0|%0, %1}" + "vpmovbq\t{%1, %0|%0, %k1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") @@ -9768,7 +9768,7 @@ (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE4_1" - "%vpmovbq\t{%1, %0|%0, %1}" + "%vpmovbq\t{%1, %0|%0, %w1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") @@ -9784,7 +9784,7 @@ (const_int 2) (const_int 3)]))))] "TARGET_AVX2" - "vpmovwq\t{%1, %0|%0, %1}" + "vpmovwq\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") @@ -9798,7 +9798,7 @@ (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE4_1" - "%vpmovwq\t{%1, %0|%0, %1}" + "%vpmovwq\t{%1, %0|%0, %k1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") @@ -9822,7 +9822,7 @@ (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE4_1" - "%vpmovdq\t{%1, %0|%0, %1}" + "%vpmovdq\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") -- 2.30.2