From 32cd58fabc29755f558eaed899a6c0684bf94adf Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Fri, 2 Apr 2021 17:43:15 -0300 Subject: [PATCH] Add VEXPAND test case for the ISA Simulator The test currently does not pass, there must be a bug somewhere. Seems like it is skipping the middle source element, as if it was doing single-pred. --- .../isa/test_caller_svp64_predication.py | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py index e595a7e3..96827e8a 100644 --- a/src/soc/decoder/isa/test_caller_svp64_predication.py +++ b/src/soc/decoder/isa/test_caller_svp64_predication.py @@ -331,6 +331,41 @@ class DecoderTestCase(FHDLTestCase): expected_regs[5] = 0xffff_ffff_ffff_ff90 # (from r9) expected_regs[6] = 0xffff_ffff_ffff_ff92 # (from r11) expected_regs[7] = 0x0 # (VL loop runs out before we can use it) + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_regs, svstate) + self._check_regs(sim, expected_regs) + + def test_intpred_vexpand(self): + # reg num 0 1 2 3 4 5 6 7 8 9 10 11 + # src always Y Y Y + # | | + # +-------+ | + # | +------+ + # | | + # dest r3=0b101 Y N Y + + isa = SVP64Asm(['sv.extsb/dm=r3 5.v, 9.v']) + lst = list(isa) + print("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[3] = 0b101 # predicate mask + initial_regs[9] = 0x90 # source is "always", so this will be used + initial_regs[10] = 0x91 # likewise + initial_regs[11] = 0x92 # the VL loop runs out before we can use it + # SVSTATE (in this case, VL=3) + svstate = SVP64State() + svstate.vl[0:7] = 3 # VL + svstate.maxvl[0:7] = 3 # MAXVL + print("SVSTATE", bin(svstate.spr.asint())) + # copy before running + expected_regs = deepcopy(initial_regs) + expected_regs[5] = 0xffff_ffff_ffff_ff90 # 1st bit of r3 is 1 + expected_regs[6] = 0x0 # skip + expected_regs[7] = 0xffff_ffff_ffff_ff91 # 3nd bit of r3 is 1 + with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate) self._check_regs(sim, expected_regs) -- 2.30.2