From 32d2d85a5af1f3cef1d5c0d7ea11036b6e675829 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 24 Aug 2020 23:27:02 +0100 Subject: [PATCH] argh, reading regfile over DMI was overlapped and corrupting reg 0 --- src/soc/litex/florent/sim.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index e4a1fbbf..688fde4b 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -285,7 +285,7 @@ class LibreSoCSim(SoCSDRAM): # read all 32 GPRs for i in range(32): - self.sync += If(active_dbg & (dmicount == 14+(i*8)), + self.sync += If(active_dbg & (dmicount == 16+(i*8)), (dmi_addr.eq(0b100), # GSPR addr dmi_din.eq(i), # r1 dmi_req.eq(1), @@ -293,7 +293,7 @@ class LibreSoCSim(SoCSDRAM): ) ) - self.sync += If(active_dbg & (dmicount == 18+(i*8)), + self.sync += If(active_dbg & (dmicount == 20+(i*8)), (dmi_addr.eq(0b101), # GSPR data dmi_req.eq(1), dmi_wen.eq(0), -- 2.30.2