From 32d3e7bd6926349bb8757a4586030a98f839062d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 28 Oct 2022 13:20:10 +0100 Subject: [PATCH] fix dsld pseudocode to use ROTL64 instead of ROTL128 --- openpower/isa/svfixedarith.mdwn | 8 ++++---- src/openpower/test/bigint/bigint_cases.py | 1 - 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn index e9e4beab..0de85f27 100644 --- a/openpower/isa/svfixedarith.mdwn +++ b/openpower/isa/svfixedarith.mdwn @@ -56,10 +56,10 @@ VA2-Form Pseudo-code: n <- (RB)[58:63] - v <- ROTL128([0]*64 || (RA), n) - mask <- ¬MASK(64, 63-n) - RT <- v[64:127] | ((RC) & mask) - RS <- v[0:63] + v <- ROTL64((RA), n) + mask <- MASK(64, 63-n) + RT <- (v[0:63] & mask) | ((RC) & ¬mask) + RS <- v[0:63] & ¬mask Special Registers Altered: diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py index 665f30b0..9abdce55 100644 --- a/src/openpower/test/bigint/bigint_cases.py +++ b/src/openpower/test/bigint/bigint_cases.py @@ -173,7 +173,6 @@ class SVP64BigIntCases(TestAccumulatorBase): svstate.vl = 3 svstate.maxvl = 3 e = ExpectedState(pc=8, int_regs=gprs) - e.intregs[5] = 0x0000_0000_0000_0000 # it's down the other end... self.add_case(prog, gprs, expected=e, initial_svstate=svstate) def case_sv_bigint_mul_by_scalar(self): -- 2.30.2