From 32db050bdcccd20dbe1437d6f81d74f3ff2c9ceb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 19 Jun 2020 03:06:41 +0100 Subject: [PATCH] do mix-in for test_sim.py so that jacob can write some div tests without having to run all the other ones --- src/soc/simulator/test_sim.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py index 9ab807d6..de4193bc 100644 --- a/src/soc/simulator/test_sim.py +++ b/src/soc/simulator/test_sim.py @@ -207,7 +207,7 @@ class GeneralTestCases(FHDLTestCase): self.test_data.append(tc) -class DecoderTestCase(GeneralTestCases): +class DecoderBase: def run_tst(self, generator, initial_mem=None): m = Module() @@ -290,5 +290,9 @@ class DecoderTestCase(GeneralTestCases): self.assertEqual(qemu_val, sim_val) +class DecoderTestCase(DecoderBase, GeneralTestCases): + pass + + if __name__ == "__main__": unittest.main() -- 2.30.2