From 32e16e23377ecbba7783e33428ebb4575b874fe5 Mon Sep 17 00:00:00 2001 From: Paul Berry Date: Fri, 23 Aug 2013 20:14:00 -0700 Subject: [PATCH] i965: rename legacy gs structs and functions to ff_gs. "ff" is for "fixed function". This frees up the name "gs" to refer to user-defined geometry shaders. Reviewed-by: Kenneth Graunke Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_context.h | 14 +- src/mesa/drivers/dri/i965/brw_gs.c | 42 +++--- src/mesa/drivers/dri/i965/brw_gs.h | 19 ++- src/mesa/drivers/dri/i965/brw_gs_emit.c | 150 ++++++++++--------- src/mesa/drivers/dri/i965/brw_gs_state.c | 17 ++- src/mesa/drivers/dri/i965/brw_misc_state.c | 10 +- src/mesa/drivers/dri/i965/brw_state.h | 2 +- src/mesa/drivers/dri/i965/brw_state_dump.c | 4 +- src/mesa/drivers/dri/i965/brw_state_upload.c | 8 +- src/mesa/drivers/dri/i965/gen6_gs_state.c | 10 +- src/mesa/drivers/dri/i965/gen6_sol.c | 12 +- src/mesa/drivers/dri/i965/gen6_urb.c | 8 +- src/mesa/drivers/dri/i965/gen7_disable.c | 2 +- src/mesa/drivers/dri/i965/gen7_urb.c | 4 +- 14 files changed, 156 insertions(+), 146 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index c456e611e04..381fe1f9edf 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -474,7 +474,7 @@ struct brw_clip_prog_data { GLuint total_grf; }; -struct brw_gs_prog_data { +struct brw_ff_gs_prog_data { GLuint urb_read_length; GLuint total_grf; @@ -678,8 +678,8 @@ enum brw_cache_id { BRW_SF_UNIT, /* scissor state on gen6 */ BRW_VS_UNIT, BRW_VS_PROG, - BRW_GS_UNIT, - BRW_GS_PROG, + BRW_FF_GS_UNIT, + BRW_FF_GS_PROG, BRW_CLIP_VP, BRW_CLIP_UNIT, BRW_CLIP_PROG, @@ -768,8 +768,8 @@ enum shader_time_shader_type { #define CACHE_NEW_SF_UNIT (1<primitive) { case _3DPRIM_QUADLIST: - brw_gs_quads( &c, key ); + brw_ff_gs_quads( &c, key ); break; case _3DPRIM_QUADSTRIP: - brw_gs_quad_strip( &c, key ); + brw_ff_gs_quad_strip( &c, key ); break; case _3DPRIM_LINELOOP: - brw_gs_lines( &c ); + brw_ff_gs_lines( &c ); break; default: ralloc_free(mem_ctx); @@ -142,16 +142,16 @@ static void compile_gs_prog( struct brw_context *brw, printf("\n"); } - brw_upload_cache(&brw->cache, BRW_GS_PROG, + brw_upload_cache(&brw->cache, BRW_FF_GS_PROG, &c.key, sizeof(c.key), program, program_size, &c.prog_data, sizeof(c.prog_data), - &brw->gs.prog_offset, &brw->gs.prog_data); + &brw->ff_gs.prog_offset, &brw->ff_gs.prog_data); ralloc_free(mem_ctx); } -static void populate_key( struct brw_context *brw, - struct brw_gs_prog_key *key ) +static void populate_key(struct brw_context *brw, + struct brw_ff_gs_prog_key *key) { static const unsigned swizzle_for_offset[4] = { BRW_SWIZZLE4(0, 1, 2, 3), @@ -225,34 +225,34 @@ static void populate_key( struct brw_context *brw, /* Calculate interpolants for triangle and line rasterization. */ static void -brw_upload_gs_prog(struct brw_context *brw) +brw_upload_ff_gs_prog(struct brw_context *brw) { - struct brw_gs_prog_key key; + struct brw_ff_gs_prog_key key; /* Populate the key: */ populate_key(brw, &key); - if (brw->gs.prog_active != key.need_gs_prog) { - brw->state.dirty.cache |= CACHE_NEW_GS_PROG; - brw->gs.prog_active = key.need_gs_prog; + if (brw->ff_gs.prog_active != key.need_gs_prog) { + brw->state.dirty.cache |= CACHE_NEW_FF_GS_PROG; + brw->ff_gs.prog_active = key.need_gs_prog; } - if (brw->gs.prog_active) { - if (!brw_search_cache(&brw->cache, BRW_GS_PROG, + if (brw->ff_gs.prog_active) { + if (!brw_search_cache(&brw->cache, BRW_FF_GS_PROG, &key, sizeof(key), - &brw->gs.prog_offset, &brw->gs.prog_data)) { - compile_gs_prog( brw, &key ); + &brw->ff_gs.prog_offset, &brw->ff_gs.prog_data)) { + compile_ff_gs_prog( brw, &key ); } } } -const struct brw_tracked_state brw_gs_prog = { +const struct brw_tracked_state brw_ff_gs_prog = { .dirty = { .mesa = (_NEW_LIGHT), .brw = (BRW_NEW_PRIMITIVE | BRW_NEW_TRANSFORM_FEEDBACK), .cache = CACHE_NEW_VS_PROG }, - .emit = brw_upload_gs_prog + .emit = brw_upload_ff_gs_prog }; diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h index 319f10521fe..695f435a52d 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.h +++ b/src/mesa/drivers/dri/i965/brw_gs.h @@ -39,7 +39,7 @@ #define MAX_GS_VERTS (4) -struct brw_gs_prog_key { +struct brw_ff_gs_prog_key { GLbitfield64 attrs; /** @@ -70,10 +70,10 @@ struct brw_gs_prog_key { unsigned char transform_feedback_swizzles[BRW_MAX_SOL_BINDINGS]; }; -struct brw_gs_compile { +struct brw_ff_gs_compile { struct brw_compile func; - struct brw_gs_prog_key key; - struct brw_gs_prog_data prog_data; + struct brw_ff_gs_prog_key key; + struct brw_ff_gs_prog_data prog_data; struct { struct brw_reg R0; @@ -102,10 +102,13 @@ struct brw_gs_compile { struct brw_vue_map vue_map; }; -void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key ); -void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key ); -void brw_gs_lines( struct brw_gs_compile *c ); -void gen6_sol_program(struct brw_gs_compile *c, struct brw_gs_prog_key *key, +void brw_ff_gs_quads(struct brw_ff_gs_compile *c, + struct brw_ff_gs_prog_key *key); +void brw_ff_gs_quad_strip(struct brw_ff_gs_compile *c, + struct brw_ff_gs_prog_key *key); +void brw_ff_gs_lines(struct brw_ff_gs_compile *c); +void gen6_sol_program(struct brw_ff_gs_compile *c, + struct brw_ff_gs_prog_key *key, unsigned num_verts, bool check_edge_flag); #endif diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c index fff3585aec4..7fff53e5c4c 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c @@ -52,9 +52,9 @@ * * - The thread will need to use the destination_indices register. */ -static void brw_gs_alloc_regs( struct brw_gs_compile *c, - GLuint nr_verts, - bool sol_program ) +static void brw_ff_gs_alloc_regs(struct brw_ff_gs_compile *c, + GLuint nr_verts, + bool sol_program) { GLuint i = 0,j; @@ -100,7 +100,7 @@ static void brw_gs_alloc_regs( struct brw_gs_compile *c, * This function sets up the above data by copying by copying the contents of * R0 to the header register. */ -static void brw_gs_initialize_header(struct brw_gs_compile *c) +static void brw_ff_gs_initialize_header(struct brw_ff_gs_compile *c) { struct brw_compile *p = &c->func; brw_MOV(p, c->reg.header, c->reg.R0); @@ -113,8 +113,8 @@ static void brw_gs_initialize_header(struct brw_gs_compile *c) * PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we * need to be able to update on a per-vertex basis. */ -static void brw_gs_overwrite_header_dw2(struct brw_gs_compile *c, - unsigned dw2) +static void brw_ff_gs_overwrite_header_dw2(struct brw_ff_gs_compile *c, + unsigned dw2) { struct brw_compile *p = &c->func; brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2)); @@ -128,7 +128,7 @@ static void brw_gs_overwrite_header_dw2(struct brw_gs_compile *c, * DWORD 2. So this function extracts the primitive type field, bitshifts it * appropriately, and stores it in c->reg.header. */ -static void brw_gs_overwrite_header_dw2_from_r0(struct brw_gs_compile *c) +static void brw_ff_gs_overwrite_header_dw2_from_r0(struct brw_ff_gs_compile *c) { struct brw_compile *p = &c->func; brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2), @@ -143,7 +143,8 @@ static void brw_gs_overwrite_header_dw2_from_r0(struct brw_gs_compile *c) * This is used to set/unset the "PrimStart" and "PrimEnd" flags appropriately * for each vertex. */ -static void brw_gs_offset_header_dw2(struct brw_gs_compile *c, int offset) +static void brw_ff_gs_offset_header_dw2(struct brw_ff_gs_compile *c, + int offset) { struct brw_compile *p = &c->func; brw_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2), @@ -163,9 +164,9 @@ static void brw_gs_offset_header_dw2(struct brw_gs_compile *c, int offset) * will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE * message. */ -static void brw_gs_emit_vue(struct brw_gs_compile *c, - struct brw_reg vert, - bool last) +static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile *c, + struct brw_reg vert, + bool last) { struct brw_compile *p = &c->func; bool allocate = !last; @@ -208,7 +209,7 @@ static void brw_gs_emit_vue(struct brw_gs_compile *c, * the allocated URB entry (which will be needed by the URB_WRITE meesage that * follows). */ -static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim) +static void brw_ff_gs_ff_sync(struct brw_ff_gs_compile *c, int num_prim) { struct brw_compile *p = &c->func; @@ -225,97 +226,100 @@ static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim) } -void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key ) +void +brw_ff_gs_quads(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key) { struct brw_context *brw = c->func.brw; - brw_gs_alloc_regs(c, 4, false); - brw_gs_initialize_header(c); + brw_ff_gs_alloc_regs(c, 4, false); + brw_ff_gs_initialize_header(c); /* Use polygons for correct edgeflag behaviour. Note that vertex 3 * is the PV for quads, but vertex 0 for polygons: */ if (brw->gen == 5) - brw_gs_ff_sync(c, 1); - brw_gs_overwrite_header_dw2( + brw_ff_gs_ff_sync(c, 1); + brw_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_START)); if (key->pv_first) { - brw_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_gs_overwrite_header_dw2( + brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0); + brw_ff_gs_overwrite_header_dw2( c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT); - brw_gs_emit_vue(c, c->reg.vertex[1], 0); - brw_gs_emit_vue(c, c->reg.vertex[2], 0); - brw_gs_overwrite_header_dw2( + brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0); + brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0); + brw_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END)); - brw_gs_emit_vue(c, c->reg.vertex[3], 1); + brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1); } else { - brw_gs_emit_vue(c, c->reg.vertex[3], 0); - brw_gs_overwrite_header_dw2( + brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0); + brw_ff_gs_overwrite_header_dw2( c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT); - brw_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_gs_emit_vue(c, c->reg.vertex[1], 0); - brw_gs_overwrite_header_dw2( + brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0); + brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0); + brw_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END)); - brw_gs_emit_vue(c, c->reg.vertex[2], 1); + brw_ff_gs_emit_vue(c, c->reg.vertex[2], 1); } } -void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key ) +void +brw_ff_gs_quad_strip(struct brw_ff_gs_compile *c, + struct brw_ff_gs_prog_key *key) { struct brw_context *brw = c->func.brw; - brw_gs_alloc_regs(c, 4, false); - brw_gs_initialize_header(c); + brw_ff_gs_alloc_regs(c, 4, false); + brw_ff_gs_initialize_header(c); if (brw->gen == 5) - brw_gs_ff_sync(c, 1); - brw_gs_overwrite_header_dw2( + brw_ff_gs_ff_sync(c, 1); + brw_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_START)); if (key->pv_first) { - brw_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_gs_overwrite_header_dw2( + brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0); + brw_ff_gs_overwrite_header_dw2( c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT); - brw_gs_emit_vue(c, c->reg.vertex[1], 0); - brw_gs_emit_vue(c, c->reg.vertex[2], 0); - brw_gs_overwrite_header_dw2( + brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0); + brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0); + brw_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END)); - brw_gs_emit_vue(c, c->reg.vertex[3], 1); + brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1); } else { - brw_gs_emit_vue(c, c->reg.vertex[2], 0); - brw_gs_overwrite_header_dw2( + brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0); + brw_ff_gs_overwrite_header_dw2( c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT); - brw_gs_emit_vue(c, c->reg.vertex[3], 0); - brw_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_gs_overwrite_header_dw2( + brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0); + brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0); + brw_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END)); - brw_gs_emit_vue(c, c->reg.vertex[1], 1); + brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1); } } -void brw_gs_lines( struct brw_gs_compile *c ) +void brw_ff_gs_lines(struct brw_ff_gs_compile *c) { struct brw_context *brw = c->func.brw; - brw_gs_alloc_regs(c, 2, false); - brw_gs_initialize_header(c); + brw_ff_gs_alloc_regs(c, 2, false); + brw_ff_gs_initialize_header(c); if (brw->gen == 5) - brw_gs_ff_sync(c, 1); - brw_gs_overwrite_header_dw2( + brw_ff_gs_ff_sync(c, 1); + brw_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_START)); - brw_gs_emit_vue(c, c->reg.vertex[0], 0); - brw_gs_overwrite_header_dw2( + brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0); + brw_ff_gs_overwrite_header_dw2( c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT) | URB_WRITE_PRIM_END)); - brw_gs_emit_vue(c, c->reg.vertex[1], 1); + brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1); } /** @@ -323,14 +327,14 @@ void brw_gs_lines( struct brw_gs_compile *c ) * (transform feedback). */ void -gen6_sol_program(struct brw_gs_compile *c, struct brw_gs_prog_key *key, +gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key, unsigned num_verts, bool check_edge_flags) { struct brw_compile *p = &c->func; c->prog_data.svbi_postincrement_value = num_verts; - brw_gs_alloc_regs(c, num_verts, true); - brw_gs_initialize_header(c); + brw_ff_gs_alloc_regs(c, num_verts, true); + brw_ff_gs_initialize_header(c); if (key->num_transform_feedback_bindings > 0) { unsigned vertex, binding; @@ -442,7 +446,7 @@ gen6_sol_program(struct brw_gs_compile *c, struct brw_gs_prog_key *key, * the register that we overwrote while streaming out transform feedback * data. */ - brw_gs_initialize_header(c); + brw_ff_gs_initialize_header(c); /* Finally, wait for the write commit to occur so that we can proceed to * other things safely. @@ -457,19 +461,21 @@ gen6_sol_program(struct brw_gs_compile *c, struct brw_gs_prog_key *key, brw_MOV(p, c->reg.temp, c->reg.temp); } - brw_gs_ff_sync(c, 1); + brw_ff_gs_ff_sync(c, 1); - brw_gs_overwrite_header_dw2_from_r0(c); + brw_ff_gs_overwrite_header_dw2_from_r0(c); switch (num_verts) { case 1: - brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START | URB_WRITE_PRIM_END); - brw_gs_emit_vue(c, c->reg.vertex[0], true); + brw_ff_gs_offset_header_dw2(c, + URB_WRITE_PRIM_START | URB_WRITE_PRIM_END); + brw_ff_gs_emit_vue(c, c->reg.vertex[0], true); break; case 2: - brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START); - brw_gs_emit_vue(c, c->reg.vertex[0], false); - brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_END - URB_WRITE_PRIM_START); - brw_gs_emit_vue(c, c->reg.vertex[1], true); + brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START); + brw_ff_gs_emit_vue(c, c->reg.vertex[0], false); + brw_ff_gs_offset_header_dw2(c, + URB_WRITE_PRIM_END - URB_WRITE_PRIM_START); + brw_ff_gs_emit_vue(c, c->reg.vertex[1], true); break; case 3: if (check_edge_flags) { @@ -482,10 +488,10 @@ gen6_sol_program(struct brw_gs_compile *c, struct brw_gs_prog_key *key, brw_imm_ud(BRW_GS_EDGE_INDICATOR_0)); brw_IF(p, BRW_EXECUTE_1); } - brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_START); - brw_gs_emit_vue(c, c->reg.vertex[0], false); - brw_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START); - brw_gs_emit_vue(c, c->reg.vertex[1], false); + brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START); + brw_ff_gs_emit_vue(c, c->reg.vertex[0], false); + brw_ff_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START); + brw_ff_gs_emit_vue(c, c->reg.vertex[1], false); if (check_edge_flags) { brw_ENDIF(p); /* Only emit vertex 2 in PRIM_END mode if this is the last triangle @@ -498,9 +504,9 @@ gen6_sol_program(struct brw_gs_compile *c, struct brw_gs_prog_key *key, brw_imm_ud(BRW_GS_EDGE_INDICATOR_1)); brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); } - brw_gs_offset_header_dw2(c, URB_WRITE_PRIM_END); + brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END); brw_set_predicate_control(p, BRW_PREDICATE_NONE); - brw_gs_emit_vue(c, c->reg.vertex[2], true); + brw_ff_gs_emit_vue(c, c->reg.vertex[2], true); break; } } diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c index bee0214eb65..98dc955f005 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_state.c +++ b/src/mesa/drivers/dri/i965/brw_gs_state.c @@ -41,20 +41,20 @@ brw_upload_gs_unit(struct brw_context *brw) struct brw_gs_unit_state *gs; gs = brw_state_batch(brw, AUB_TRACE_GS_STATE, - sizeof(*gs), 32, &brw->gs.state_offset); + sizeof(*gs), 32, &brw->ff_gs.state_offset); memset(gs, 0, sizeof(*gs)); /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_GS_PROG */ - if (brw->gs.prog_active) { - gs->thread0.grf_reg_count = (ALIGN(brw->gs.prog_data->total_grf, 16) / + if (brw->ff_gs.prog_active) { + gs->thread0.grf_reg_count = (ALIGN(brw->ff_gs.prog_data->total_grf, 16) / 16 - 1); gs->thread0.kernel_start_pointer = brw_program_reloc(brw, - brw->gs.state_offset + + brw->ff_gs.state_offset + offsetof(struct brw_gs_unit_state, thread0), - brw->gs.prog_offset + + brw->ff_gs.prog_offset + (gs->thread0.grf_reg_count << 1)) >> 6; gs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; @@ -64,7 +64,8 @@ brw_upload_gs_unit(struct brw_context *brw) gs->thread3.const_urb_entry_read_offset = 0; gs->thread3.const_urb_entry_read_length = 0; gs->thread3.urb_entry_read_offset = 0; - gs->thread3.urb_entry_read_length = brw->gs.prog_data->urb_read_length; + gs->thread3.urb_entry_read_length = + brw->ff_gs.prog_data->urb_read_length; /* BRW_NEW_URB_FENCE */ gs->thread4.nr_urb_entries = brw->urb.nr_gs_entries; @@ -82,7 +83,7 @@ brw_upload_gs_unit(struct brw_context *brw) if (unlikely(INTEL_DEBUG & DEBUG_STATS)) gs->thread4.stats_enable = 1; - brw->state.dirty.cache |= CACHE_NEW_GS_UNIT; + brw->state.dirty.cache |= CACHE_NEW_FF_GS_UNIT; } const struct brw_tracked_state brw_gs_unit = { @@ -92,7 +93,7 @@ const struct brw_tracked_state brw_gs_unit = { BRW_NEW_PROGRAM_CACHE | BRW_NEW_CURBE_OFFSETS | BRW_NEW_URB_FENCE), - .cache = CACHE_NEW_GS_PROG + .cache = CACHE_NEW_FF_GS_PROG }, .emit = brw_upload_gs_unit, }; diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index ac7f1f414fe..3492ea9eaed 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -114,7 +114,7 @@ static void upload_gen6_binding_table_pointers(struct brw_context *brw) GEN6_BINDING_TABLE_MODIFY_PS | (4 - 2)); OUT_BATCH(brw->vs.bind_bo_offset); /* vs */ - OUT_BATCH(brw->gs.bind_bo_offset); /* gs */ + OUT_BATCH(brw->ff_gs.bind_bo_offset); /* gs */ OUT_BATCH(brw->wm.bind_bo_offset); /* wm/ps */ ADVANCE_BATCH(); } @@ -151,9 +151,9 @@ static void upload_pipelined_state_pointers(struct brw_context *brw ) OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2)); OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, brw->vs.state_offset); - if (brw->gs.prog_active) + if (brw->ff_gs.prog_active) OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, - brw->gs.state_offset | 1); + brw->ff_gs.state_offset | 1); else OUT_BATCH(0); OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, @@ -183,8 +183,8 @@ const struct brw_tracked_state brw_psp_urb_cbs = { BRW_NEW_BATCH | BRW_NEW_STATE_BASE_ADDRESS), .cache = (CACHE_NEW_VS_UNIT | - CACHE_NEW_GS_UNIT | - CACHE_NEW_GS_PROG | + CACHE_NEW_FF_GS_UNIT | + CACHE_NEW_FF_GS_PROG | CACHE_NEW_CLIP_UNIT | CACHE_NEW_SF_UNIT | CACHE_NEW_WM_UNIT | diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 0127e107e3c..85f82fe81e1 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -52,7 +52,7 @@ extern const struct brw_tracked_state brw_constant_buffer; extern const struct brw_tracked_state brw_curbe_offsets; extern const struct brw_tracked_state brw_invariant_state; extern const struct brw_tracked_state brw_fs_samplers; -extern const struct brw_tracked_state brw_gs_prog; +extern const struct brw_tracked_state brw_ff_gs_prog; extern const struct brw_tracked_state brw_gs_unit; extern const struct brw_tracked_state brw_line_stipple; extern const struct brw_tracked_state brw_aa_line_parameters; diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c b/src/mesa/drivers/dri/i965/brw_state_dump.c index a42a0491f59..5c117bb0965 100644 --- a/src/mesa/drivers/dri/i965/brw_state_dump.c +++ b/src/mesa/drivers/dri/i965/brw_state_dump.c @@ -498,8 +498,8 @@ dump_prog_cache(struct brw_context *brw) case BRW_VS_PROG: name = "VS kernel"; break; - case BRW_GS_PROG: - name = "GS kernel"; + case BRW_FF_GS_PROG: + name = "Fixed-function GS kernel"; break; case BRW_CLIP_PROG: name = "CLIP kernel"; diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 64e0bcf8e8f..b8830024827 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -40,7 +40,7 @@ static const struct brw_tracked_state *gen4_atoms[] = { &brw_vs_prog, /* must do before GS prog, state base address. */ - &brw_gs_prog, /* must do before state base address */ + &brw_ff_gs_prog, /* must do before state base address */ &brw_interpolation_map, @@ -108,7 +108,7 @@ static const struct brw_tracked_state *gen4_atoms[] = static const struct brw_tracked_state *gen6_atoms[] = { &brw_vs_prog, /* must do before state base address */ - &brw_gs_prog, /* must do before state base address */ + &brw_ff_gs_prog, /* must do before state base address */ &brw_wm_prog, /* must do before state base address */ &gen6_clip_vp, @@ -405,8 +405,8 @@ static struct dirty_bit_map cache_bits[] = { DEFINE_BIT(CACHE_NEW_SF_UNIT), DEFINE_BIT(CACHE_NEW_VS_UNIT), DEFINE_BIT(CACHE_NEW_VS_PROG), - DEFINE_BIT(CACHE_NEW_GS_UNIT), - DEFINE_BIT(CACHE_NEW_GS_PROG), + DEFINE_BIT(CACHE_NEW_FF_GS_UNIT), + DEFINE_BIT(CACHE_NEW_FF_GS_PROG), DEFINE_BIT(CACHE_NEW_CLIP_VP), DEFINE_BIT(CACHE_NEW_CLIP_UNIT), DEFINE_BIT(CACHE_NEW_CLIP_PROG), diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c index 5f32bf9bb6c..ac7828680bf 100644 --- a/src/mesa/drivers/dri/i965/gen6_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c @@ -42,21 +42,21 @@ upload_gs_state(struct brw_context *brw) OUT_BATCH(0); ADVANCE_BATCH(); - if (brw->gs.prog_active) { + if (brw->ff_gs.prog_active) { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); - OUT_BATCH(brw->gs.prog_offset); + OUT_BATCH(brw->ff_gs.prog_offset); OUT_BATCH(GEN6_GS_SPF_MODE | GEN6_GS_VECTOR_MASK_ENABLE); OUT_BATCH(0); /* no scratch space */ OUT_BATCH((2 << GEN6_GS_DISPATCH_START_GRF_SHIFT) | - (brw->gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT)); + (brw->ff_gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT)); OUT_BATCH(((brw->max_gs_threads - 1) << GEN6_GS_MAX_THREADS_SHIFT) | GEN6_GS_STATISTICS_ENABLE | GEN6_GS_SO_STATISTICS_ENABLE | GEN6_GS_RENDERING_ENABLE); OUT_BATCH(GEN6_GS_SVBI_PAYLOAD_ENABLE | GEN6_GS_SVBI_POSTINCREMENT_ENABLE | - (brw->gs.prog_data->svbi_postincrement_value << + (brw->ff_gs.prog_data->svbi_postincrement_value << GEN6_GS_SVBI_POSTINCREMENT_VALUE_SHIFT) | GEN6_GS_ENABLE); ADVANCE_BATCH(); @@ -82,7 +82,7 @@ const struct brw_tracked_state gen6_gs_state = { .dirty = { .mesa = _NEW_TRANSFORM, .brw = BRW_NEW_CONTEXT, - .cache = CACHE_NEW_GS_PROG + .cache = CACHE_NEW_FF_GS_PROG }, .emit = upload_gs_state, }; diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c b/src/mesa/drivers/dri/i965/gen6_sol.c index 5c294b1d768..ced9bb90736 100644 --- a/src/mesa/drivers/dri/i965/gen6_sol.c +++ b/src/mesa/drivers/dri/i965/gen6_sol.c @@ -56,11 +56,11 @@ gen6_update_sol_surfaces(struct brw_context *brw) xfb_obj->Offset[buffer] / 4 + linked_xfb_info->Outputs[i].DstOffset; brw_update_sol_surface( - brw, xfb_obj->Buffers[buffer], &brw->gs.surf_offset[surf_index], + brw, xfb_obj->Buffers[buffer], &brw->ff_gs.surf_offset[surf_index], linked_xfb_info->Outputs[i].NumComponents, linked_xfb_info->BufferStride[buffer], buffer_offset); } else { - brw->gs.surf_offset[surf_index] = 0; + brw->ff_gs.surf_offset[surf_index] = 0; } } @@ -101,9 +101,9 @@ brw_gs_upload_binding_table(struct brw_context *brw) /* Skip making a binding table if we don't have anything to put in it. */ if (!has_surfaces) { - if (brw->gs.bind_bo_offset != 0) { + if (brw->ff_gs.bind_bo_offset != 0) { brw->state.dirty.brw |= BRW_NEW_GS_BINDING_TABLE; - brw->gs.bind_bo_offset = 0; + brw->ff_gs.bind_bo_offset = 0; } return; } @@ -113,10 +113,10 @@ brw_gs_upload_binding_table(struct brw_context *brw) */ bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE, sizeof(uint32_t) * BRW_MAX_GS_SURFACES, - 32, &brw->gs.bind_bo_offset); + 32, &brw->ff_gs.bind_bo_offset); /* BRW_NEW_SURFACES */ - memcpy(bind, brw->gs.surf_offset, BRW_MAX_GS_SURFACES * sizeof(uint32_t)); + memcpy(bind, brw->ff_gs.surf_offset, BRW_MAX_GS_SURFACES * sizeof(uint32_t)); brw->state.dirty.brw |= BRW_NEW_GS_BINDING_TABLE; } diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c index 8bb0d1b0a3b..e16d30aa13a 100644 --- a/src/mesa/drivers/dri/i965/gen6_urb.c +++ b/src/mesa/drivers/dri/i965/gen6_urb.c @@ -64,7 +64,7 @@ gen6_upload_urb( struct brw_context *brw ) unsigned gs_size = vs_size; /* Calculate how many entries fit in each stage's section of the URB */ - if (brw->gs.prog_active) { + if (brw->ff_gs.prog_active) { nr_vs_entries = (total_urb_size/2) / (vs_size * 128); nr_gs_entries = (total_urb_size/2) / (gs_size * 128); } else { @@ -109,16 +109,16 @@ gen6_upload_urb( struct brw_context *brw ) * doesn't exist on Gen6). So for now we just do a full pipeline flush as * a workaround. */ - if (brw->urb.gen6_gs_previously_active && !brw->gs.prog_active) + if (brw->urb.gen6_gs_previously_active && !brw->ff_gs.prog_active) intel_batchbuffer_emit_mi_flush(brw); - brw->urb.gen6_gs_previously_active = brw->gs.prog_active; + brw->urb.gen6_gs_previously_active = brw->ff_gs.prog_active; } const struct brw_tracked_state gen6_urb = { .dirty = { .mesa = 0, .brw = BRW_NEW_CONTEXT, - .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG), + .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_FF_GS_PROG), }, .emit = gen6_upload_urb, }; diff --git a/src/mesa/drivers/dri/i965/gen7_disable.c b/src/mesa/drivers/dri/i965/gen7_disable.c index c9564c69614..860aa951df0 100644 --- a/src/mesa/drivers/dri/i965/gen7_disable.c +++ b/src/mesa/drivers/dri/i965/gen7_disable.c @@ -29,7 +29,7 @@ static void disable_stages(struct brw_context *brw) { - assert(!brw->gs.prog_active); + assert(!brw->ff_gs.prog_active); /* Disable the Geometry Shader (GS) Unit */ BEGIN_BATCH(7); diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c index 350f644dfcd..927af3782a2 100644 --- a/src/mesa/drivers/dri/i965/gen7_urb.c +++ b/src/mesa/drivers/dri/i965/gen7_urb.c @@ -93,7 +93,7 @@ gen7_upload_urb(struct brw_context *brw) assert(brw->urb.nr_vs_entries % 8 == 0); assert(brw->urb.nr_gs_entries % 8 == 0); /* GS requirement */ - assert(!brw->gs.prog_active); + assert(!brw->ff_gs.prog_active); gen7_emit_vs_workaround_flush(brw); gen7_emit_urb_state(brw, brw->urb.nr_vs_entries, vs_size, brw->urb.vs_start); @@ -128,7 +128,7 @@ const struct brw_tracked_state gen7_urb = { .dirty = { .mesa = 0, .brw = BRW_NEW_CONTEXT, - .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG), + .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_FF_GS_PROG), }, .emit = gen7_upload_urb, }; -- 2.30.2