From 32eed2d43d4f9616b3bb1c9f88c184c3e955995e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 15 Jun 2020 20:05:32 +0100 Subject: [PATCH] have to set up addr/st rel-go link before setting up nmigen Simulator LD/ST now works in test_core.py --- src/soc/simple/test/test_core.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 8b633c7b..ccc7f7de 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -70,13 +70,14 @@ class TestRunner(FHDLTestCase): comb += pdecode2.dec.raw_opcode_in.eq(instruction) comb += core.ivalid_i.eq(ivalid_i) - sim = Simulator(m) # temporary hack: says "go" immediately for both address gen and ST ldst = core.fus.fus['ldst0'] m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel + # nmigen Simulation + sim = Simulator(m) sim.add_clock(1e-6) def process(): @@ -226,7 +227,7 @@ class TestRunner(FHDLTestCase): if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() - #suite.addTest(TestRunner(LDSTTestCase.test_data)) + suite.addTest(TestRunner(LDSTTestCase.test_data)) suite.addTest(TestRunner(CRTestCase.test_data)) suite.addTest(TestRunner(ShiftRotTestCase.test_data)) suite.addTest(TestRunner(LogicalTestCase.test_data)) -- 2.30.2