From 332a5d7a3f28f1c8b1231959085f1421e5c0c535 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 12 May 2017 23:12:12 -0700 Subject: [PATCH] intel/isl: Add support for setting component write disables Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl.h | 20 ++++++++++++++++++++ src/intel/isl/isl_surface_state.c | 6 ++++++ 2 files changed, 26 insertions(+) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 8131f45ae47..acc9e77d3e7 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -589,6 +589,21 @@ typedef uint64_t isl_surf_usage_flags_t; #define ISL_SURF_USAGE_CCS_BIT (1u << 15) /** @} */ +/** + * @defgroup Channel Mask + * + * These #define values are chosen to match the values of + * RENDER_SURFACE_STATE::Color Buffer Component Write Disables + * + * @{ + */ +typedef uint8_t isl_channel_mask_t; +#define ISL_CHANNEL_BLUE_BIT (1 << 0) +#define ISL_CHANNEL_GREEN_BIT (1 << 1) +#define ISL_CHANNEL_RED_BIT (1 << 2) +#define ISL_CHANNEL_ALPHA_BIT (1 << 3) +/** @} */ + /** * @brief A channel select (also known as texture swizzle) value */ @@ -1009,6 +1024,11 @@ struct isl_surf_fill_state_info { */ union isl_color_value clear_color; + /** + * Surface write disables for gen4-5 + */ + isl_channel_mask_t write_disables; + /* Intra-tile offset */ uint16_t x_offset_sa, y_offset_sa; }; diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index fa464694862..d63b245ef23 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -256,6 +256,12 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.SurfaceFormat = info->view->format; +#if GEN_GEN <= 5 + s.ColorBufferComponentWriteDisables = info->write_disables; +#else + assert(info->write_disables == 0); +#endif + #if GEN_IS_HASWELL s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat); #endif -- 2.30.2