From 333d8f61a21edd364b966ab8aa70e232ccdc4810 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Tue, 6 May 2008 10:39:51 +0200 Subject: [PATCH] mmx.md: Remove double backslashes from asm templates. * config/i386/mmx.md: Remove double backslashes from asm templates. (*addv2sf3): Rename from mmx_addv2sf3 insn pattern. (mmx_addv2sf3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*mulv2sf3): Rename from mmx_mulv2sf3 insn pattern. (mmx_mulv2sf3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*v2sf3_finite): New insn pattern. (*v2sf3): Rename from mmx_v2sf3 insn pattern. (mmx_v2sf3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (mmx_3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*3): New insn pattern. (mmx_add3): Removed. (mmx_ssadd3): Ditto. (mmx_usadd3): Ditto. (mmx_sub3): Ditto. (mmx_sssub3): Ditto. (mmx_ussub3): Ditto. (*mulv4hi3): Rename from mmx_mulv4hi3 insn pattern. (mmx_mulv4hi3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*smulv4hi3_highpart): Rename from mmx_smulv4hi3_highpart insn pattern. (mmx_smulv4hi3_highpart): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*umulv4hi3_highpart): Rename from mmx_umulv4hi3_highpart insn pattern. (mmx_umulv4hi3_highpart): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*v4hi3): Rename from mmx_v4hi3 insn pattern. (mmx_v4hi3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*v8qi3): Rename from mmx_v8qi3 insn pattern. (mmx_v8qi3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. (*3): Rename from mmx_3 insn pattern. (mmx_3): New expander. Use ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. From-SVN: r134976 --- gcc/ChangeLog | 51 +++++++- gcc/config/i386/mmx.md | 265 ++++++++++++++++++++++++++--------------- 2 files changed, 218 insertions(+), 98 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 448a8950d2f..930772c9d85 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,46 @@ +2008-05-06 Uros Bizjak + + * config/i386/mmx.md: Remove double backslashes from asm templates. + (*addv2sf3): Rename from mmx_addv2sf3 insn pattern. + (mmx_addv2sf3): New expander. Use ix86_fixup_binary_operands_no_copy + to handle nonimmediate operands. + (*mulv2sf3): Rename from mmx_mulv2sf3 insn pattern. + (mmx_mulv2sf3): New expander. Use ix86_fixup_binary_operands_no_copy + to handle nonimmediate operands. + (*v2sf3_finite): New insn pattern. + (*v2sf3): Rename from mmx_v2sf3 insn pattern. + (mmx_v2sf3): New expander. Use + ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. + (mmx_3): New expander. Use + ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. + (*3): New insn pattern. + (mmx_add3): Removed. + (mmx_ssadd3): Ditto. + (mmx_usadd3): Ditto. + (mmx_sub3): Ditto. + (mmx_sssub3): Ditto. + (mmx_ussub3): Ditto. + (*mulv4hi3): Rename from mmx_mulv4hi3 insn pattern. + (mmx_mulv4hi3): New expander. Use ix86_fixup_binary_operands_no_copy + to handle nonimmediate operands. + (*smulv4hi3_highpart): Rename from mmx_smulv4hi3_highpart + insn pattern. + (mmx_smulv4hi3_highpart): New expander. Use + ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. + (*umulv4hi3_highpart): Rename from mmx_umulv4hi3_highpart + insn pattern. + (mmx_umulv4hi3_highpart): New expander. Use + ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. + (*v4hi3): Rename from mmx_v4hi3 insn pattern. + (mmx_v4hi3): New expander. Use + ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. + (*v8qi3): Rename from mmx_v8qi3 insn pattern. + (mmx_v8qi3): New expander. Use + ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. + (*3): Rename from mmx_3 insn pattern. + (mmx_3): New expander. Use + ix86_fixup_binary_operands_no_copy to handle nonimmediate operands. + 2008-05-05 Jan Hubicka PR tree-optimization/36118 @@ -6,8 +49,8 @@ 2008-05-05 Andrew Pinski PR middle-end/36141 - * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Don't create VCE - for function decls. + * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Don't create + VCE for function decls. 2008-05-05 H.J. Lu @@ -55,9 +98,9 @@ Generalize UNUSED macro. (__gthread_once): Add. (__gthread_key_create): Add. - (__gthread_key_delete): Add. + (__gthread_key_delete): Add. (__gthread_getspecific): Add. - (__gthread_setspecific): Add. + (__gthread_setspecific): Add. 2008-05-05 Andrew Pinski diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index bfcddc6614b..32cec069bca 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1,5 +1,5 @@ ;; GCC machine description for MMX and 3dNOW! instructions -;; Copyright (C) 2005, 2007 +;; Copyright (C) 2005, 2007, 2008 ;; Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -212,12 +212,20 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn "mmx_addv2sf3" +(define_expand "mmx_addv2sf3" + [(set (match_operand:V2SF 0 "register_operand" "") + (plus:V2SF + (match_operand:V2SF 1 "nonimmediate_operand" "") + (match_operand:V2SF 2 "nonimmediate_operand" "")))] + "TARGET_3DNOW" + "ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);") + +(define_insn "*addv2sf3" [(set (match_operand:V2SF 0 "register_operand" "=y") (plus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0") (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] "TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)" - "pfadd\\t{%2, %0|%0, %2}" + "pfadd\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "V2SF")]) @@ -227,8 +235,8 @@ (match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))] "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ - pfsub\\t{%2, %0|%0, %2} - pfsubr\\t{%2, %0|%0, %2}" + pfsub\t{%2, %0|%0, %2} + pfsubr\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "V2SF")]) @@ -239,22 +247,56 @@ "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "") -(define_insn "mmx_mulv2sf3" +(define_expand "mmx_mulv2sf3" + [(set (match_operand:V2SF 0 "register_operand" "") + (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "") + (match_operand:V2SF 2 "nonimmediate_operand" "")))] + "TARGET_3DNOW" + "ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);") + +(define_insn "*mulv2sf3" [(set (match_operand:V2SF 0 "register_operand" "=y") (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0") (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)" - "pfmul\\t{%2, %0|%0, %2}" + "pfmul\t{%2, %0|%0, %2}" [(set_attr "type" "mmxmul") (set_attr "mode" "V2SF")]) -(define_insn "mmx_v2sf3" +;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX +;; isn't really correct, as those rtl operators aren't defined when +;; applied to NaNs. Hopefully the optimizers won't get too smart on us. + +(define_expand "mmx_v2sf3" + [(set (match_operand:V2SF 0 "register_operand" "") + (smaxmin:V2SF + (match_operand:V2SF 1 "nonimmediate_operand" "") + (match_operand:V2SF 2 "nonimmediate_operand" "")))] + "TARGET_3DNOW" +{ + if (!flag_finite_math_only) + operands[1] = force_reg (V2SFmode, operands[1]); + ix86_fixup_binary_operands_no_copy (, V2SFmode, operands); +}) + +(define_insn "*v2sf3_finite" [(set (match_operand:V2SF 0 "register_operand" "=y") (smaxmin:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0") (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] - "TARGET_3DNOW && ix86_binary_operator_ok (SMAX, V2SFmode, operands)" - "pf\\t{%2, %0|%0, %2}" + "TARGET_3DNOW && flag_finite_math_only + && ix86_binary_operator_ok (, V2SFmode, operands)" + "pf\t{%2, %0|%0, %2}" + [(set_attr "type" "mmxadd") + (set_attr "mode" "V2SF")]) + +(define_insn "*v2sf3" + [(set (match_operand:V2SF 0 "register_operand" "=y") + (smaxmin:V2SF + (match_operand:V2SF 1 "register_operand" "0") + (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] + "TARGET_3DNOW" + "pf\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "V2SF")]) @@ -263,7 +305,7 @@ (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] UNSPEC_PFRCP))] "TARGET_3DNOW" - "pfrcp\\t{%1, %0|%0, %1}" + "pfrcp\t{%1, %0|%0, %1}" [(set_attr "type" "mmx") (set_attr "mode" "V2SF")]) @@ -273,7 +315,7 @@ (match_operand:V2SF 2 "nonimmediate_operand" "ym")] UNSPEC_PFRCPIT1))] "TARGET_3DNOW" - "pfrcpit1\\t{%2, %0|%0, %2}" + "pfrcpit1\t{%2, %0|%0, %2}" [(set_attr "type" "mmx") (set_attr "mode" "V2SF")]) @@ -283,7 +325,7 @@ (match_operand:V2SF 2 "nonimmediate_operand" "ym")] UNSPEC_PFRCPIT2))] "TARGET_3DNOW" - "pfrcpit2\\t{%2, %0|%0, %2}" + "pfrcpit2\t{%2, %0|%0, %2}" [(set_attr "type" "mmx") (set_attr "mode" "V2SF")]) @@ -292,7 +334,7 @@ (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] UNSPEC_PFRSQRT))] "TARGET_3DNOW" - "pfrsqrt\\t{%1, %0|%0, %1}" + "pfrsqrt\t{%1, %0|%0, %1}" [(set_attr "type" "mmx") (set_attr "mode" "V2SF")]) @@ -302,7 +344,7 @@ (match_operand:V2SF 2 "nonimmediate_operand" "ym")] UNSPEC_PFRSQIT1))] "TARGET_3DNOW" - "pfrsqit1\\t{%2, %0|%0, %2}" + "pfrsqit1\t{%2, %0|%0, %2}" [(set_attr "type" "mmx") (set_attr "mode" "V2SF")]) @@ -320,7 +362,7 @@ (parallel [(const_int 0)])) (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))] "TARGET_3DNOW" - "pfacc\\t{%2, %0|%0, %2}" + "pfacc\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "V2SF")]) @@ -338,7 +380,7 @@ (parallel [(const_int 0)])) (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))] "TARGET_3DNOW_A" - "pfnacc\\t{%2, %0|%0, %2}" + "pfnacc\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "V2SF")]) @@ -351,7 +393,7 @@ (minus:V2SF (match_dup 1) (match_dup 2)) (const_int 1)))] "TARGET_3DNOW_A" - "pfpnacc\\t{%2, %0|%0, %2}" + "pfpnacc\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "V2SF")]) @@ -366,7 +408,7 @@ (gt:V2SI (match_operand:V2SF 1 "register_operand" "0") (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] "TARGET_3DNOW" - "pfcmpgt\\t{%2, %0|%0, %2}" + "pfcmpgt\t{%2, %0|%0, %2}" [(set_attr "type" "mmxcmp") (set_attr "mode" "V2SF")]) @@ -375,7 +417,7 @@ (ge:V2SI (match_operand:V2SF 1 "register_operand" "0") (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] "TARGET_3DNOW" - "pfcmpge\\t{%2, %0|%0, %2}" + "pfcmpge\t{%2, %0|%0, %2}" [(set_attr "type" "mmxcmp") (set_attr "mode" "V2SF")]) @@ -384,7 +426,7 @@ (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0") (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)" - "pfcmpeq\\t{%2, %0|%0, %2}" + "pfcmpeq\t{%2, %0|%0, %2}" [(set_attr "type" "mmxcmp") (set_attr "mode" "V2SF")]) @@ -398,7 +440,7 @@ [(set (match_operand:V2SI 0 "register_operand" "=y") (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))] "TARGET_3DNOW" - "pf2id\\t{%1, %0|%0, %1}" + "pf2id\t{%1, %0|%0, %1}" [(set_attr "type" "mmxcvt") (set_attr "mode" "V2SF")]) @@ -409,7 +451,7 @@ (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))] "TARGET_3DNOW_A" - "pf2iw\\t{%1, %0|%0, %1}" + "pf2iw\t{%1, %0|%0, %1}" [(set_attr "type" "mmxcvt") (set_attr "mode" "V2SF")]) @@ -420,7 +462,7 @@ (truncate:V2HI (match_operand:V2SI 1 "nonimmediate_operand" "ym")))))] "TARGET_3DNOW_A" - "pi2fw\\t{%1, %0|%0, %1}" + "pi2fw\t{%1, %0|%0, %1}" [(set_attr "type" "mmxcvt") (set_attr "mode" "V2SF")]) @@ -428,7 +470,7 @@ [(set (match_operand:V2SF 0 "register_operand" "=y") (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))] "TARGET_3DNOW" - "pi2fd\\t{%1, %0|%0, %1}" + "pi2fd\t{%1, %0|%0, %1}" [(set_attr "type" "mmxcvt") (set_attr "mode" "V2SF")]) @@ -443,7 +485,7 @@ (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym") (parallel [(const_int 1) (const_int 0)])))] "TARGET_3DNOW_A" - "pswapd\\t{%1, %0|%0, %1}" + "pswapd\t{%1, %0|%0, %1}" [(set_attr "type" "mmxcvt") (set_attr "mode" "V2SF")]) @@ -550,68 +592,51 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn "mmx_add3" +(define_expand "mmx_3" + [(set (match_operand:MMXMODEI8 0 "register_operand" "") + (plusminus:MMXMODEI8 + (match_operand:MMXMODEI8 1 "nonimmediate_operand" "") + (match_operand:MMXMODEI8 2 "nonimmediate_operand" "")))] + "TARGET_MMX || (TARGET_SSE2 && mode == V1DImode)" + "ix86_fixup_binary_operands_no_copy (, mode, operands);") + +(define_insn "*3" [(set (match_operand:MMXMODEI8 0 "register_operand" "=y") - (plus:MMXMODEI8 - (match_operand:MMXMODEI8 1 "nonimmediate_operand" "%0") + (plusminus:MMXMODEI8 + (match_operand:MMXMODEI8 1 "nonimmediate_operand" "0") (match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym")))] "(TARGET_MMX || (TARGET_SSE2 && mode == V1DImode)) - && ix86_binary_operator_ok (PLUS, mode, operands)" - "padd\t{%2, %0|%0, %2}" + && ix86_binary_operator_ok (, mode, operands)" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "DI")]) -(define_insn "mmx_ssadd3" - [(set (match_operand:MMXMODE12 0 "register_operand" "=y") - (ss_plus:MMXMODE12 - (match_operand:MMXMODE12 1 "nonimmediate_operand" "%0") - (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))] +(define_expand "mmx_3" + [(set (match_operand:MMXMODE12 0 "register_operand" "") + (sat_plusminus:MMXMODE12 + (match_operand:MMXMODE12 1 "nonimmediate_operand" "") + (match_operand:MMXMODE12 2 "nonimmediate_operand" "")))] "TARGET_MMX" - "padds\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) - -(define_insn "mmx_usadd3" - [(set (match_operand:MMXMODE12 0 "register_operand" "=y") - (us_plus:MMXMODE12 - (match_operand:MMXMODE12 1 "nonimmediate_operand" "%0") - (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX" - "paddus\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) - -(define_insn "mmx_sub3" - [(set (match_operand:MMXMODEI8 0 "register_operand" "=y") - (minus:MMXMODEI8 - (match_operand:MMXMODEI8 1 "register_operand" "0") - (match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym")))] - "(TARGET_MMX || (TARGET_SSE2 && mode == V1DImode))" - "psub\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "mmx_sssub3" +(define_insn "*3" [(set (match_operand:MMXMODE12 0 "register_operand" "=y") - (ss_minus:MMXMODE12 - (match_operand:MMXMODE12 1 "register_operand" "0") + (sat_plusminus:MMXMODE12 + (match_operand:MMXMODE12 1 "nonimmediate_operand" "0") (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX" - "psubs\t{%2, %0|%0, %2}" + "TARGET_MMX && ix86_binary_operator_ok (, mode, operands)" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "DI")]) -(define_insn "mmx_ussub3" - [(set (match_operand:MMXMODE12 0 "register_operand" "=y") - (us_minus:MMXMODE12 - (match_operand:MMXMODE12 1 "register_operand" "0") - (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))] +(define_expand "mmx_mulv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "") + (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "") + (match_operand:V4HI 2 "nonimmediate_operand" "")))] "TARGET_MMX" - "psubus\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") -(define_insn "mmx_mulv4hi3" +(define_insn "*mulv4hi3" [(set (match_operand:V4HI 0 "register_operand" "=y") (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0") (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] @@ -620,28 +645,56 @@ [(set_attr "type" "mmxmul") (set_attr "mode" "DI")]) -(define_insn "mmx_smulv4hi3_highpart" +(define_expand "mmx_smulv4hi3_highpart" + [(set (match_operand:V4HI 0 "register_operand" "") + (truncate:V4HI + (lshiftrt:V4SI + (mult:V4SI + (sign_extend:V4SI + (match_operand:V4HI 1 "nonimmediate_operand" "")) + (sign_extend:V4SI + (match_operand:V4HI 2 "nonimmediate_operand" ""))) + (const_int 16))))] + "TARGET_MMX" + "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") + +(define_insn "*smulv4hi3_highpart" [(set (match_operand:V4HI 0 "register_operand" "=y") (truncate:V4HI - (lshiftrt:V4SI - (mult:V4SI (sign_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "%0")) - (sign_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) - (const_int 16))))] + (lshiftrt:V4SI + (mult:V4SI + (sign_extend:V4SI + (match_operand:V4HI 1 "nonimmediate_operand" "%0")) + (sign_extend:V4SI + (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) + (const_int 16))))] "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)" "pmulhw\t{%2, %0|%0, %2}" [(set_attr "type" "mmxmul") (set_attr "mode" "DI")]) -(define_insn "mmx_umulv4hi3_highpart" +(define_expand "mmx_umulv4hi3_highpart" + [(set (match_operand:V4HI 0 "register_operand" "") + (truncate:V4HI + (lshiftrt:V4SI + (mult:V4SI + (zero_extend:V4SI + (match_operand:V4HI 1 "nonimmediate_operand" "")) + (zero_extend:V4SI + (match_operand:V4HI 2 "nonimmediate_operand" ""))) + (const_int 16))))] + "TARGET_SSE || TARGET_3DNOW_A" + "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") + +(define_insn "*umulv4hi3_highpart" [(set (match_operand:V4HI 0 "register_operand" "=y") (truncate:V4HI - (lshiftrt:V4SI - (mult:V4SI (zero_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "%0")) - (zero_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) + (lshiftrt:V4SI + (mult:V4SI + (zero_extend:V4SI + (match_operand:V4HI 1 "nonimmediate_operand" "%0")) + (zero_extend:V4SI + (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) (const_int 16))))] "(TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (MULT, V4HImode, operands)" @@ -687,7 +740,7 @@ (const_int 32768) (const_int 32768)])) (const_int 16))))] "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)" - "pmulhrw\\t{%2, %0|%0, %2}" + "pmulhrw\t{%2, %0|%0, %2}" [(set_attr "type" "mmxmul") (set_attr "mode" "DI")]) @@ -707,24 +760,40 @@ [(set_attr "type" "mmxmul") (set_attr "mode" "DI")]) -(define_insn "mmx_v4hi3" +(define_expand "mmx_v4hi3" + [(set (match_operand:V4HI 0 "register_operand" "") + (smaxmin:V4HI + (match_operand:V4HI 1 "nonimmediate_operand" "") + (match_operand:V4HI 2 "nonimmediate_operand" "")))] + "TARGET_SSE || TARGET_3DNOW_A" + "ix86_fixup_binary_operands_no_copy (, V4HImode, operands);") + +(define_insn "*v4hi3" [(set (match_operand:V4HI 0 "register_operand" "=y") (smaxmin:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0") (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] "(TARGET_SSE || TARGET_3DNOW_A) - && ix86_binary_operator_ok (SMAX, V4HImode, operands)" + && ix86_binary_operator_ok (, V4HImode, operands)" "pw\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "DI")]) -(define_insn "mmx_v8qi3" +(define_expand "mmx_v8qi3" + [(set (match_operand:V8QI 0 "register_operand" "") + (umaxmin:V8QI + (match_operand:V8QI 1 "nonimmediate_operand" "") + (match_operand:V8QI 2 "nonimmediate_operand" "")))] + "TARGET_SSE || TARGET_3DNOW_A" + "ix86_fixup_binary_operands_no_copy (, V8QImode, operands);") + +(define_insn "*v8qi3" [(set (match_operand:V8QI 0 "register_operand" "=y") (umaxmin:V8QI (match_operand:V8QI 1 "nonimmediate_operand" "%0") (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] "(TARGET_SSE || TARGET_3DNOW_A) - && ix86_binary_operator_ok (UMIN, V8QImode, operands)" + && ix86_binary_operator_ok (, V8QImode, operands)" "pb\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "DI")]) @@ -801,7 +870,15 @@ [(set_attr "type" "mmxadd") (set_attr "mode" "DI")]) -(define_insn "mmx_3" +(define_expand "mmx_3" + [(set (match_operand:MMXMODEI 0 "register_operand" "") + (plogic:MMXMODEI + (match_operand:MMXMODEI 1 "nonimmediate_operand" "") + (match_operand:MMXMODEI 2 "nonimmediate_operand" "")))] + "TARGET_MMX" + "ix86_fixup_binary_operands_no_copy (, mode, operands);") + +(define_insn "*3" [(set (match_operand:MMXMODEI 0 "register_operand" "=y") (plogic:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0") @@ -1017,7 +1094,7 @@ (match_operand:V2SI 1 "nonimmediate_operand" "ym") (parallel [(const_int 1) (const_int 0)])))] "TARGET_3DNOW_A" - "pswapd\\t{%1, %0|%0, %1}" + "pswapd\t{%1, %0|%0, %1}" [(set_attr "type" "mmxcvt") (set_attr "mode" "DI")]) @@ -1221,7 +1298,7 @@ if (TARGET_SSE || TARGET_3DNOW_A) return "pavgb\t{%2, %0|%0, %2}"; else - return "pavgusb\\t{%2, %0|%0, %2}"; + return "pavgusb\t{%2, %0|%0, %2}"; } [(set_attr "type" "mmxshft") (set_attr "mode" "DI")]) -- 2.30.2