From 3362d76470c5b397b53a699130406f422b83bba7 Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Mon, 16 May 2016 11:01:36 +0000 Subject: [PATCH] This patch fixes the attributes of integer immediate shifts which were... This patch fixes the attributes of integer immediate shifts which were incorrectly modelled as register controlled shifts. Also change EXTR attribute to being a rotate. * gcc/config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_3): Split integer shifts into shift_reg and bfm. (aarch64_lshr_sisd_or_int_3): Likewise. (aarch64_ashr_sisd_or_int_3): Likewise. (ror3_insn): Likewise. (si3_insn_uxtw): Likewise. (3_insn): Change to rotate_imm. (extr5_insn_alt): Likewise. (extrsi5_insn_uxtw): Likewise. (extrsi5_insn_uxtw_alt): Likewise. From-SVN: r236278 --- gcc/ChangeLog | 13 +++++++ gcc/config/aarch64/aarch64.md | 65 +++++++++++++++++++---------------- 2 files changed, 49 insertions(+), 29 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 88e39abaf17..da58116d841 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2016-05-16 Wilco Dijkstra + + * gcc/config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_3): + Split integer shifts into shift_reg and bfm. + (aarch64_lshr_sisd_or_int_3): Likewise. + (aarch64_ashr_sisd_or_int_3): Likewise. + (ror3_insn): Likewise. + (si3_insn_uxtw): Likewise. + (3_insn): Change to rotate_imm. + (extr5_insn_alt): Likewise. + (extrsi5_insn_uxtw): Likewise. + (extrsi5_insn_uxtw_alt): Likewise. + 2016-05-16 Matthew Wahab * doc/tm.texi: Regenerate. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 9b282f13388..f6bc12dd2ef 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3936,33 +3936,35 @@ ;; Logical left shift using SISD or Integer instruction (define_insn "*aarch64_ashl_sisd_or_int_3" - [(set (match_operand:GPI 0 "register_operand" "=r,w,w") - (ashift:GPI - (match_operand:GPI 1 "register_operand" "r,w,w") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "rUs,Us,w")))] + [(set (match_operand:GPI 0 "register_operand" "=r,r,w,w") + (ashift:GPI + (match_operand:GPI 1 "register_operand" "r,r,w,w") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "Us,r,Us,w")))] "" "@ + lsl\t%0, %1, %2 lsl\t%0, %1, %2 shl\t%0, %1, %2 ushl\t%0, %1, %2" - [(set_attr "simd" "no,yes,yes") - (set_attr "type" "shift_reg,neon_shift_imm, neon_shift_reg")] + [(set_attr "simd" "no,no,yes,yes") + (set_attr "type" "bfm,shift_reg,neon_shift_imm, neon_shift_reg")] ) ;; Logical right shift using SISD or Integer instruction (define_insn "*aarch64_lshr_sisd_or_int_3" - [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w") - (lshiftrt:GPI - (match_operand:GPI 1 "register_operand" "r,w,w,w") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "rUs,Us,w,0")))] + [(set (match_operand:GPI 0 "register_operand" "=r,r,w,&w,&w") + (lshiftrt:GPI + (match_operand:GPI 1 "register_operand" "r,r,w,w,w") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "Us,r,Us,w,0")))] "" "@ + lsr\t%0, %1, %2 lsr\t%0, %1, %2 ushr\t%0, %1, %2 # #" - [(set_attr "simd" "no,yes,yes,yes") - (set_attr "type" "shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] + [(set_attr "simd" "no,no,yes,yes,yes") + (set_attr "type" "bfm,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] ) (define_split @@ -3997,18 +3999,19 @@ ;; Arithmetic right shift using SISD or Integer instruction (define_insn "*aarch64_ashr_sisd_or_int_3" - [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w") + [(set (match_operand:GPI 0 "register_operand" "=r,r,w,&w,&w") (ashiftrt:GPI - (match_operand:GPI 1 "register_operand" "r,w,w,w") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "rUs,Us,w,0")))] + (match_operand:GPI 1 "register_operand" "r,r,w,w,w") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "Us,r,Us,w,0")))] "" "@ + asr\t%0, %1, %2 asr\t%0, %1, %2 sshr\t%0, %1, %2 # #" - [(set_attr "simd" "no,yes,yes,yes") - (set_attr "type" "shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] + [(set_attr "simd" "no,no,yes,yes,yes") + (set_attr "type" "bfm,shift_reg,neon_shift_imm,neon_shift_reg,neon_shift_reg")] ) (define_split @@ -4100,21 +4103,25 @@ [(set (match_operand:GPI 0 "register_operand" "=r,r") (rotatert:GPI (match_operand:GPI 1 "register_operand" "r,r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "r,Us")))] + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "Us,r")))] "" - "ror\\t%0, %1, %2" - [(set_attr "type" "shift_reg, rotate_imm")] + "@ + ror\\t%0, %1, %2 + ror\\t%0, %1, %2" + [(set_attr "type" "rotate_imm,shift_reg")] ) ;; zero_extend version of above (define_insn "*si3_insn_uxtw" - [(set (match_operand:DI 0 "register_operand" "=r") + [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (SHIFT:SI - (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss"))))] + (match_operand:SI 1 "register_operand" "r,r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "Uss,r"))))] "" - "\\t%w0, %w1, %w2" - [(set_attr "type" "shift_reg")] + "@ + \\t%w0, %w1, %2 + \\t%w0, %w1, %w2" + [(set_attr "type" "bfm,shift_reg")] ) (define_insn "*3_insn" @@ -4138,7 +4145,7 @@ "UINTVAL (operands[3]) < GET_MODE_BITSIZE (mode) && (UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (mode))" "extr\\t%0, %1, %2, %4" - [(set_attr "type" "shift_imm")] + [(set_attr "type" "rotate_imm")] ) ;; There are no canonicalisation rules for ashift and lshiftrt inside an ior @@ -4153,7 +4160,7 @@ && (UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (mode))" "extr\\t%0, %1, %2, %4" - [(set_attr "type" "shift_imm")] + [(set_attr "type" "rotate_imm")] ) ;; zero_extend version of the above @@ -4167,7 +4174,7 @@ "UINTVAL (operands[3]) < 32 && (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)" "extr\\t%w0, %w1, %w2, %4" - [(set_attr "type" "shift_imm")] + [(set_attr "type" "rotate_imm")] ) (define_insn "*extrsi5_insn_uxtw_alt" @@ -4180,7 +4187,7 @@ "UINTVAL (operands[3]) < 32 && (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)" "extr\\t%w0, %w1, %w2, %4" - [(set_attr "type" "shift_imm")] + [(set_attr "type" "rotate_imm")] ) (define_insn "*ror3_insn" -- 2.30.2