From 33801860dc942743764b323fc31550318fbf1602 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Sun, 12 Jul 2020 19:45:11 -0700 Subject: [PATCH] clean up DivPipeCoreConfig API --- src/ieee754/div_rem_sqrt_rsqrt/core.py | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index c4076266..e2042cfd 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -69,14 +69,17 @@ class DivPipeCoreConfig: self.fract_width = fract_width self.log2_radix = log2_radix if supported is None: - supported = [DP.SqrtRem, DP.UDivRem, DP.RSqrtRem] + supported = frozenset(DP) + else: + supported = frozenset(supported) self.supported = supported print(f"{self}: n_stages={self.n_stages}") def __repr__(self): """ Get repr. """ return f"DivPipeCoreConfig({self.bit_width}, " \ - + f"{self.fract_width}, {self.log2_radix})" + + f"{self.fract_width}, {self.log2_radix}, "\ + + f"supported={self.supported})" @property def n_stages(self): @@ -150,7 +153,7 @@ class DivPipeCoreInterstageData: """ Create a ``DivPipeCoreInterstageData`` instance. """ self.core_config = core_config bw = core_config.bit_width - if core_config.supported == [DP.UDivRem]: + if core_config.supported == {DP.UDivRem}: self.compare_len = bw * 2 else: self.compare_len = bw * 3 @@ -197,7 +200,7 @@ class DivPipeCoreOutputData: """ Create a ``DivPipeCoreOutputData`` instance. """ self.core_config = core_config bw = core_config.bit_width - if core_config.supported == [DP.UDivRem]: + if core_config.supported == {DP.UDivRem}: self.compare_len = bw * 2 else: self.compare_len = bw * 3 @@ -225,7 +228,7 @@ class DivPipeCoreSetupStage(Elaboratable): self.i = self.ispec() self.o = self.ospec() bw = core_config.bit_width - if core_config.supported == [DP.UDivRem]: + if core_config.supported == {DP.UDivRem}: self.compare_len = bw * 2 else: self.compare_len = bw * 3 @@ -281,7 +284,7 @@ class Trial(Elaboratable): self.current_shift = current_shift self.log2_radix = log2_radix bw = core_config.bit_width - if core_config.supported == [DP.UDivRem]: + if core_config.supported == {DP.UDivRem}: self.compare_len = bw * 2 else: self.compare_len = bw * 3 @@ -370,7 +373,7 @@ class DivPipeCoreCalculateStage(Elaboratable): assert stage_index in range(core_config.n_stages) self.core_config = core_config bw = core_config.bit_width - if core_config.supported == [DP.UDivRem]: + if core_config.supported == {DP.UDivRem}: self.compare_len = bw * 2 else: self.compare_len = bw * 3 -- 2.30.2