From 33a200d9298962244e532d1b6e04c7ae6c677ac6 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 29 Mar 2023 14:50:21 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls010.mdwn | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index e30326f2b..dfabbaeef 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -42,7 +42,37 @@ svp64 fits into the "reserved" portions of the v3.1 prefix, making it possible f Subset implementations in hardware are permitted, as long as certain rules are followed, allowing for full soft-emulation including future -revisions. Details in the [[svp64/appendix]]. +revisions. Compliancy Subsets exist to ensure minimum levels of binary +interoperability expectations within certain environments. + +## Register files, elements, and Element-width Overrides + +In the Upper Compliancy Levels the size of the GPR and FPR Register files are expanded +from 32 to 128 entries, and the number of CR Fields expanded from CR0-CR7 to CR0-CR127. + +``` + #pragma pack + typedef union { + uint8_t b[]; + uint16_t s[]; + uint32_t i[]; + uint64_t l[]; + uint8_t actual_bytes[8]; + } el_reg_t; + + elreg_t int_regfile[128]; +``` + +Hardware Architectural note: to avoid a Read-Modify-Write at the register file it is +strongly recommended to implement byte-level write-enable lines exactly as has been +implemented in DRAM ICs for many decades. Additionally the predicate mask bit is advised +to be associated with the element operation and ultimately passed to the register file. +When element-width is set to 64-bit the relevant predicate mask bit may be repeated +eight times and pull all eight write-port byte-level lines HIGH. Clearly when element-width +is set to 8-bit the relevant predicate mask bit corresponds directly with one single +byte-level write-enable line. It is up to the Hardware Architect to then amortise (merge) +elements together into both PredicatedSIMD Pipelines as well as simultaneous non-overlapping +Register File writesto achieve High Performance designs. ## SVP64 encoding features -- 2.30.2