From 3401c9c1e875cdc1d3f3d444e0dc8509d73df004 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 21:59:11 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 6cbc0ef66..db230e0b2 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -626,8 +626,12 @@ the Coherent Memory accesses. This design is almost identical to the early Vector Processors of the late 1950s and early 1960s, which also critically relied -on implicit auto-increment addressing. The barrel-architecture neatly -solves one of the inherent problems of those early designs ( a mismatch in memory +on implicit auto-increment addressing. +The [CDC STAR-100](https://en.m.wikipedia.org/wiki/CDC_STAR-100) +for example was specifically designed as a Memory-to-Memory Vector +Processor. The barrel-architecture of Snitch neatly +solves one of the inherent problems of those early designs (a mismatch +with memory speed) and the presence of a full register file caters for a second limitation of pure Memory-based Vector Processors: temporary variables needed in the computation of intermediate results, which -- 2.30.2