From 342c9178a611ea7ba84cd0e000b39e97ecfe6961 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 8 Sep 2022 23:46:04 +0100 Subject: [PATCH] whitespace --- src/openpower/sv/trans/svp64.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 3d8cd327..7b146fb4 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -883,8 +883,8 @@ class SVP64Asm: # encode SV-CR 3-bit field into extra, v3.0field. # 3-bit is for things like BF and BFA elif rtype == 'CR_3bit': - sv_extra, field = crf_extra(etype, - rname, extra_idx, regmode, field, extras) + sv_extra, field = crf_extra(etype, rname, extra_idx, + regmode, field, extras) # encode SV-CR 5-bit field into extra, v3.0field # 5-bit is for things like BA BB BC BT etc. @@ -894,8 +894,8 @@ class SVP64Asm: cr_subfield = field & 0b11 # record bottom 2 bits for later field = field >> 2 # strip bottom 2 bits # use the exact same 3-bit function for the top 3 bits - sv_extra, field = crf_extra(etype, - rname, extra_idx, regmode, field, extras) + sv_extra, field = crf_extra(etype, rname, extra_idx, + regmode, field, extras) # reconstruct the actual 5-bit CR field (preserving the # bottom 2 bits, unaltered) field = (field << 2) | cr_subfield -- 2.30.2