From 345cb8bd79a856eb13e691bd20f523327bec15bc Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 5 May 2022 15:25:41 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 57a3bca3f..6e1859324 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -36,10 +36,14 @@ ARM's SVE/SVE2 is critically flawed (lacking the Cray `setvl` instruction that makes a truly ubiquitous Vector ISA) in ways that will become apparent over time as adoption increases. In the meantime programmers are, in direct violation of ARM's advice on how to use SVE2, trying desperately -to use it as if it was Packed SIMD NEON. +to use it as if it was Packed SIMD NEON. The advice not to create SVE2 +assembler that is hardcoded to fixed widths is being disregarded, in +favour of writing *multiple identical implementations* of a function, +each with a different hardware width, and compelling software to choose +one at runtime after probing the hardware. Even RISC-V, for all that we can be grateful to the RISC-V Founders for -reviving Cray Vectors, has severe performance and imolementation +reviving Cray Vectors, has severe performance and implementation limitations that are only really apparent to exceptionally experienced assembly-level developers with a wide, diverse depth in multiple ISAs: one of the best and clearest is a @@ -54,6 +58,12 @@ on its viability for high performance use. That is not to say that its use in low-performance embedded scenarios is not ideal: in private custom secretive commercial usage it is perfect. Ubiquitous and common everyday usage in scenarios currently occupied by ARM, Intel, -AMD and IBM: not so much. Thus, even though RISC-V has Cray-style Vectors, -the ISA is, unfortunately, fundamentally flawed. +AMD and IBM? not so much. Thus, even though RISC-V has Cray-style Vectors, +the whole ISA is, unfortunately, fundamentally flawed as far as power +efficient high performance is concerned. + +Slowly, at this point, a realisation should be sinking in that, actually, +there aren't as many really truly viable Vector ISAs out there, as the +ones that are evolving in the general direction of Vectorisation are, +in various completely different ways, flawed. -- 2.30.2