From 3499182b3a7c2035645d09f8e973be5c68e30776 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 17:45:41 +0100 Subject: [PATCH] test actual reg values being produced in core test --- src/soc/decoder/selectable_int.py | 3 +++ src/soc/simple/test/test_core.py | 15 ++++++--------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py index 02f0ca83..80eebf48 100644 --- a/src/soc/decoder/selectable_int.py +++ b/src/soc/decoder/selectable_int.py @@ -363,6 +363,9 @@ class SelectableInt: def __len__(self): return self.bits + def asint(self): + return self.value + def onebit(bit): return SelectableInt(1 if bit else 0, 1) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 877c215e..5ec289dc 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -13,8 +13,8 @@ from soc.simple.core import NonProductionCore from soc.experiment.compalu_multi import find_ok # hack # test with ALU data and Logical data -#from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase, test_data -from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, test_data +from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase, test_data +#from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, test_data def set_cu_input(cu, idx, data): @@ -176,13 +176,10 @@ class TestRunner(FHDLTestCase): rval = yield core.regs.int.regs[i].reg intregs.append(rval) print ("int regs", intregs) - if False: - yield Settle() - # get all outputs (one by one, just "because") - res = yield from get_cu_outputs(cu, code) - - yield from self.iodef.check_cu_outputs(res, pdecode2, - sim, code) + for i in range(32): + simregval = sim.gpr[i].asint() + self.assertEqual(simregval, intregs[i], + "int reg %d not equal %s" % (i, repr(code))) sim.add_sync_process(process) with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw", -- 2.30.2