From 34a62bfe0c6f1e7a6c23bc99d5a9879765b5ad48 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 6 Nov 2023 20:38:18 -0800 Subject: [PATCH] System Call Interrupts do *not* set SRR1[TRAP] See PowerISA v3.1B Book III 7.5.14 --- openpower/isa/system.mdwn | 2 +- src/openpower/decoder/isa/test_syscall.py | 3 ++- src/openpower/test/trap/trap_cases.py | 13 ++++++++----- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/openpower/isa/system.mdwn b/openpower/isa/system.mdwn index 958502d3..0c41078e 100644 --- a/openpower/isa/system.mdwn +++ b/openpower/isa/system.mdwn @@ -18,7 +18,7 @@ Pseudo-code: SRR1[0:32] <- MSR[0:32] SRR1[37:41] <- MSR[37:41] SRR1[48:63] <- MSR[48:63] - TRAP(0xC00) + TRAP(0xC00, None) Special Registers Altered: diff --git a/src/openpower/decoder/isa/test_syscall.py b/src/openpower/decoder/isa/test_syscall.py index a1f42ba2..2bbd27da 100644 --- a/src/openpower/decoder/isa/test_syscall.py +++ b/src/openpower/decoder/isa/test_syscall.py @@ -42,7 +42,8 @@ class SyscallTestCase(FHDLTestCase): SRR1[0:33] = MSR[0:33] SRR1[37:42] = MSR[37:42] SRR1[48:64] = MSR[48:64] - SRR1[PIb.TRAP] = 1 + # PowerISA v3.1B Book III 7.5.14 specifies TRAP is set to zero + SRR1[PIb.TRAP] = 0 # rfid instruction MSR[51] = MSR[3] & SRR1[51] | ~MSR[3] & MSR[51] diff --git a/src/openpower/test/trap/trap_cases.py b/src/openpower/test/trap/trap_cases.py index b90bf693..13d9b094 100644 --- a/src/openpower/test/trap/trap_cases.py +++ b/src/openpower/test/trap/trap_cases.py @@ -2,7 +2,7 @@ from openpower.simulator.program import Program from openpower.endian import bigendian from openpower.consts import MSR from openpower.test.state import ExpectedState - +from openpower.decoder.selectable_int import SelectableInt from openpower.test.common import TestAccumulatorBase import random @@ -62,7 +62,7 @@ class TrapTestCase(TestAccumulatorBase): e = ExpectedState(pc=0xc00) e.intregs[1] = 1 e.sprs['SRR0'] = 4 # PC to return to: CIA+4 - e.sprs['SRR1'] = 0x9000000000022903 # MSR to restore after sc return + e.sprs['SRR1'] = 0x9000000000002903 # MSR to restore after sc return e.msr = 0x9000000000000001 # MSR changed to this by sc/trap self.add_case(Program(lst, bigendian), initial_regs, initial_sprs, @@ -86,9 +86,12 @@ class TrapTestCase(TestAccumulatorBase): e.intregs[1] = 1 # should be unaltered e.intregs[0] = 2 # due to instruction at 0xc0c e.sprs['SRR0'] = 0xc0c # PC to return to: CIA+4 (0xc0c) - e.sprs['SRR1'] = 0xffff_ffff_ffff_ffff # MSR after rfid return - e.msr = 0xffffffffffffffff # MSR is restored (by rfid) - e.pc = 0xc10 # should stop after addi 0,0,2 + SRR1 = SelectableInt(-1, 64) + SRR1[33:37] = 0 # sc clears bits 33:36 + SRR1[42:48] = 0 # sc clears bits 42:47 + e.sprs['SRR1'] = int(SRR1) # MSR after rfid return + e.msr = 0xffff_ffff_ffff_ffff # MSR is restored (by rfid) + e.pc = 0xc10 # should stop after addi 0,0,2 self.add_case(Program(lst, bigendian), initial_regs, initial_sprs, initial_msr=0xffff_ffff_ffff_ffff, -- 2.30.2