From 34ee6af3e85e5ecf845fde177f62e3d65e697f19 Mon Sep 17 00:00:00 2001 From: Emily Brickey Date: Tue, 4 Aug 2020 12:20:06 -0700 Subject: [PATCH] arch: update port terminology Change-Id: Ifcf90534d8e5ff5fc68538ec87dc541517ea404d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32311 Reviewed-by: Bobby R. Bruce Reviewed-by: Giacomo Travaglini Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/arch/arm/ArmTLB.py | 2 +- src/arch/generic/BaseTLB.py | 2 +- src/arch/riscv/RiscvTLB.py | 2 +- src/arch/riscv/pagetable_walker.hh | 4 ++-- src/arch/x86/X86LocalApic.py | 6 +++--- src/arch/x86/X86TLB.py | 2 +- src/arch/x86/pagetable_walker.hh | 4 ++-- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 721d0623a..a821a048d 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -54,7 +54,7 @@ class ArmTableWalker(ClockedObject): # to the Stage2MMU, and shared by the two table walkers, but we # access it through the ITB and DTB walked objects in the CPU for # symmetry with the other ISAs. - port = MasterPort("Port used by the two table walkers") + port = RequestPort("Port used by the two table walkers") sys = Param.System(Parent.any, "system object parameter") diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py index 02776e6ad..cca7da6a5 100644 --- a/src/arch/generic/BaseTLB.py +++ b/src/arch/generic/BaseTLB.py @@ -34,4 +34,4 @@ class BaseTLB(SimObject): cxx_header = "arch/generic/tlb.hh" # Ports to connect with other TLB levels slave = VectorSlavePort("Port closer to the CPU side") - master = MasterPort("Port closer to memory side") + master = RequestPort("Port closer to memory side") diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py index 884b71fa4..4844febc6 100644 --- a/src/arch/riscv/RiscvTLB.py +++ b/src/arch/riscv/RiscvTLB.py @@ -37,7 +37,7 @@ class RiscvPagetableWalker(ClockedObject): type = 'RiscvPagetableWalker' cxx_class = 'RiscvISA::Walker' cxx_header = 'arch/riscv/pagetable_walker.hh' - port = MasterPort("Port for the hardware table walker") + port = RequestPort("Port for the hardware table walker") system = Param.System(Parent.any, "system object") num_squash_per_cycle = Param.Unsigned(4, "Number of outstanding walks that can be squashed per cycle") diff --git a/src/arch/riscv/pagetable_walker.hh b/src/arch/riscv/pagetable_walker.hh index 60826a055..d9ab569c7 100644 --- a/src/arch/riscv/pagetable_walker.hh +++ b/src/arch/riscv/pagetable_walker.hh @@ -58,11 +58,11 @@ namespace RiscvISA { protected: // Port for accessing memory - class WalkerPort : public MasterPort + class WalkerPort : public RequestPort { public: WalkerPort(const std::string &_name, Walker * _walker) : - MasterPort(_name, _walker), walker(_walker) + RequestPort(_name, _walker), walker(_walker) {} protected: diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py index a28f6f3d2..442a5e17e 100644 --- a/src/arch/x86/X86LocalApic.py +++ b/src/arch/x86/X86LocalApic.py @@ -48,11 +48,11 @@ class X86LocalApic(BaseInterrupts): type = 'X86LocalApic' cxx_class = 'X86ISA::Interrupts' cxx_header = 'arch/x86/interrupts.hh' - int_master = MasterPort("Port for sending interrupt messages") - int_slave = SlavePort("Port for receiving interrupt messages") + int_master = RequestPort("Port for sending interrupt messages") + int_slave = ResponsePort("Port for receiving interrupt messages") int_latency = Param.Latency('1ns', \ "Latency for an interrupt to propagate through this device.") - pio = SlavePort("Programmed I/O port") + pio = ResponsePort("Programmed I/O port") system = Param.System(Parent.any, "System this device is part of") pio_latency = Param.Latency('100ns', 'Programmed IO latency') diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index bb35526cf..d9dd9802c 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -43,7 +43,7 @@ class X86PagetableWalker(ClockedObject): type = 'X86PagetableWalker' cxx_class = 'X86ISA::Walker' cxx_header = 'arch/x86/pagetable_walker.hh' - port = MasterPort("Port for the hardware table walker") + port = RequestPort("Port for the hardware table walker") system = Param.System(Parent.any, "system object") num_squash_per_cycle = Param.Unsigned(4, "Number of outstanding walks that can be squashed per cycle") diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh index a269426d9..55bb09873 100644 --- a/src/arch/x86/pagetable_walker.hh +++ b/src/arch/x86/pagetable_walker.hh @@ -57,11 +57,11 @@ namespace X86ISA { protected: // Port for accessing memory - class WalkerPort : public MasterPort + class WalkerPort : public RequestPort { public: WalkerPort(const std::string &_name, Walker * _walker) : - MasterPort(_name, _walker), walker(_walker) + RequestPort(_name, _walker), walker(_walker) {} protected: -- 2.30.2