From 353efaa5922c08c320e034feabf5517c7d453b3f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 12 Jul 2022 10:30:21 +0100 Subject: [PATCH] add FRS as destination to PowerDecoder2 DecodeOut --- src/openpower/decoder/power_decoder2.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 7ac8c4b4..cc2be39e 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -385,7 +385,7 @@ class DecodeC(Elaboratable): class DecodeOut(Elaboratable): """DecodeOut from instruction - decodes output register RA, RT or SPR + decodes output register RA, RT, FRS, FRT, or SPR """ def __init__(self, dec, op, regreduce_en): @@ -412,6 +412,9 @@ class DecodeOut(Elaboratable): # select Register out field with m.Switch(self.sel_in): + with m.Case(OutSel.FRS): + comb += reg.data.eq(self.dec.FRS) + comb += reg.ok.eq(1) with m.Case(OutSel.FRT): comb += reg.data.eq(self.dec.FRT) comb += reg.ok.eq(1) -- 2.30.2