From 354bcb847915a4a2465d91529a1eef8bf9eca24a Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 8 May 2022 16:18:53 +0100
Subject: [PATCH]

---
 openpower/sv/SimpleV_rationale.mdwn | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index f0b6b8664..35ef65f22 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -882,7 +882,10 @@ ZOLC capability in order to compact binary size to the bare minimum.
 
 One key strategic question does remain: do the PEs need to have
 a RADIX MMU and associated TLB-aware minimal L1 Cache, in order
-to support OpenCAPI properly?
+to support OpenCAPI properly? The saving grace here is that with
+the expectation of running only hot-loops with ZOLC-driven
+binaries, the size of L1 Cache needed would be miniscule compared
+to the average high-end CPU.
 
 **Roadmap summary of Advanced SVP64**
 
-- 
2.30.2