From 3565881c9a5cc3fc6688cf9f08765f6e9252f389 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 21 Jul 2019 21:24:47 +0100
Subject: [PATCH] match mantissa width up in div config

---
 src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py |  6 ++++--
 src/ieee754/fpdiv/div0.py                  | 19 ++++++++++++++-----
 src/ieee754/fpdiv/pipeline.py              |  5 +++++
 3 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
index 7146b574..28eacbd6 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@ -132,8 +132,10 @@ class DivPipeBaseStage:
         m.d.comb += self.o.ctx.eq(self.i.ctx)
 
     def get_core_config(self):
-        width = self.pspec.width
-        return DivPipeCoreConfig(width+2, 0, 1)
+        m_width = self.pspec.m_width # mantissa width
+        # 4 extra bits on the mantissa: MSB is zero, MSB-1 is 1
+        # then there is guard and round at the LSB end
+        return DivPipeCoreConfig(m_width+4, 0, log_radix=2)
 
 
 class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 90c98847..5f30d632 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -1,4 +1,4 @@
-"""IEEE754 Floating Point Divider 
+"""IEEE754 Floating Point Divider
 
 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
 """
@@ -82,11 +82,20 @@ class FPDivStage0Mod(Elaboratable):
             # result is therefore 0.4999999 (0.5/0.99999) and 1.9999998
             # (0.99999/0.5).
 
+            # zero-extend the mantissas (room for sticky/guard)
+            # plus the extra MSB.  See DivPipeBaseStage.get_core_config
+            am0 = Signal(len(self.i.a.m)+3, reset_less=True)
+            bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
+            m.d.comb += [
+                         am0.eq(Cat(0, 0, self.i.a.m, 0)),
+                         bm0.eq(Cat(0, 0, self.i.b.m, 0))
+                        ]
+
             m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
-                         self.o.dividend.eq(self.i.a.m), # TODO: check
-                         self.o.divisor_radicand.eq(self.i.b.m), # TODO: check
-                         self.o.operation.eq(Const(0)) # TODO (set from ctx.op)
+                         self.o.dividend.eq(am0), # TODO: check
+                         self.o.divisor_radicand.eq(bm0), # TODO: check
+                         self.o.operation.eq(Const(0)) # TODO check: DIV
                 ]
 
         # these are required and must not be touched
@@ -98,7 +107,7 @@ class FPDivStage0Mod(Elaboratable):
 
 
 class FPDivStage0(FPState):
-    """ First stage of div.  
+    """ First stage of div.
     """
 
     def __init__(self, pspec):
diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 3473e4c6..5bdbaf5f 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -141,6 +141,11 @@ class FPDIVMuxInOut(ReservationStations):
     def __init__(self, width, num_rows, op_wid=0):
         self.id_wid = num_bits(width)
         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
+        # get the standard mantissa width, store in the pspec
+        # (used in DivPipeBaseStage.get_core_config)
+        p = FPFormat.standard(width)
+        self.pspec.m_width = p.m_width
+
         # XXX TODO - a class (or function?) that takes the pspec (right here)
         # and creates... "something".  that "something" MUST have an eq function
         # new_pspec = deepcopy(self.pspec)
-- 
2.30.2