From 35718780c42dc4b95105165a616796251ad36169 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 25 Oct 2020 15:50:42 +0000 Subject: [PATCH] update non_generated add.il for convenience --- experiments10/add.py | 5 +- experiments10/non_generated/add.il | 970 +++++++++++++++-------------- 2 files changed, 498 insertions(+), 477 deletions(-) diff --git a/experiments10/add.py b/experiments10/add.py index 551b277..73e4092 100644 --- a/experiments10/add.py +++ b/experiments10/add.py @@ -19,7 +19,7 @@ class ADD(Elaboratable): self.f = Signal(width) # set up JTAG - self.jtag = TAP(ir_width=4) + self.jtag = TAP(ir_width=3) self.jtag.bus.tck.name = 'tck' self.jtag.bus.tms.name = 'tms' self.jtag.bus.tdo.name = 'tdo' @@ -28,6 +28,9 @@ class ADD(Elaboratable): # have to create at least one shift register self.sr = self.jtag.add_shiftreg(ircode=4, length=3) + # sigh and one iotype + self.ios = self.jtag.add_io(name="test", iotype=IOType.In) + def elaborate(self, platform): m = Module() diff --git a/experiments10/non_generated/add.il b/experiments10/non_generated/add.il index 2de11d3..e936889 100644 --- a/experiments10/non_generated/add.il +++ b/experiments10/non_generated/add.il @@ -1,12 +1,12 @@ attribute \generator "nMigen" attribute \nmigen.hierarchy "add.jtag._fsm" module \_fsm - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire width 1 output 0 \capture attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire width 1 output 1 \isdr + wire width 1 output 0 \isdr attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:23" wire width 1 \isdr$next + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire width 1 output 1 \capture attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:25" wire width 1 output 2 \shift attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:26" @@ -17,12 +17,16 @@ module \_fsm wire width 1 \isir$next attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire width 1 output 5 \posjtag_rst + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire width 1 output 6 \negjtag_rst attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire width 1 output 6 \posjtag_clk + wire width 1 output 7 \posjtag_clk + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire width 1 output 8 \negjtag_clk attribute \src "add.py:22" - wire width 1 input 7 \tck + wire width 1 input 9 \tck attribute \src "add.py:22" - wire width 1 input 8 \tms + wire width 1 input 10 \tms attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:49" wire width 1 \local_clk process $group_0 @@ -37,15 +41,11 @@ module \_fsm assign \posjtag_rst \rst sync init end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire width 1 \negjtag_clk process $group_2 assign \negjtag_clk 1'0 assign \negjtag_clk \tck sync init end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire width 1 \negjtag_rst process $group_3 assign \negjtag_rst 1'0 assign \negjtag_rst \rst @@ -513,21 +513,21 @@ attribute \generator "nMigen" attribute \nmigen.hierarchy "add.jtag._irblock" module \_irblock attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:127" - wire width 4 output 0 \ir + wire width 3 output 0 \ir attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:127" - wire width 4 \ir$next + wire width 3 \ir$next attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24" wire width 1 input 1 \capture attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:25" wire width 1 input 2 \shift attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire width 1 input 3 \update + attribute \src "add.py:22" + wire width 1 input 4 \tdi attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:22" - wire width 1 input 4 \isir + wire width 1 input 5 \isir attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:128" - wire width 1 output 5 \tdo - attribute \src "add.py:22" - wire width 1 input 6 \tdi + wire width 1 output 6 \tdo attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire width 1 input 7 \posjtag_rst attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28" @@ -538,9 +538,9 @@ module \_irblock sync init end attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:138" - wire width 4 \shift_ir + wire width 3 \shift_ir attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:138" - wire width 4 \shift_ir$next + wire width 3 \shift_ir$next attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:366" wire width 1 $1 attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:366" @@ -589,12 +589,12 @@ module \_irblock assign \shift_ir$next \ir attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:143" case 3'-1- - assign \shift_ir$next { \tdi \shift_ir [3:1] } + assign \shift_ir$next { \tdi \shift_ir [2:1] } attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:145" case 3'1-- end sync init - update \shift_ir 4'0000 + update \shift_ir 3'000 sync posedge \posjtag_clk update \shift_ir \shift_ir$next end @@ -652,10 +652,10 @@ module \_irblock attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530" switch \posjtag_rst case 1'1 - assign \ir$next 4'0001 + assign \ir$next 3'001 end sync init - update \ir 4'0001 + update \ir 3'001 sync posedge \posjtag_clk update \ir \ir$next end @@ -663,20 +663,20 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "add.jtag._idblock" module \_idblock - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:127" - wire width 4 input 0 \ir + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire width 1 input 0 \select_id + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire width 1 input 1 \id_bypass attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire width 1 input 1 \capture - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire width 1 input 2 \isdr + wire width 1 input 2 \capture attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:25" wire width 1 input 3 \shift attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire width 1 input 4 \update - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:225" - wire width 1 output 5 \jtag_id_tdo attribute \src "add.py:22" - wire width 1 input 6 \tdi + wire width 1 input 5 \tdi + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:225" + wire width 1 output 6 \jtag_id_tdo attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire width 1 input 7 \posjtag_rst attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28" @@ -690,238 +690,69 @@ module \_idblock end attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:240" wire width 1 \_capture - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:383" wire width 1 $1 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $eq $2 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 1'1 - parameter \Y_WIDTH 1'1 - connect \A \ir - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $3 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $eq $4 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 3'100 - parameter \Y_WIDTH 1'1 - connect \A \ir - connect \B 4'1111 - connect \Y $3 - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $5 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $or $6 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 1'1 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 1'1 - parameter \Y_WIDTH 1'1 - connect \A $1 - connect \B $3 - connect \Y $5 - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $7 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $and $8 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 1'1 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 1'1 - parameter \Y_WIDTH 1'1 - connect \A \isdr - connect \B $5 - connect \Y $7 - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:379" - wire width 1 $9 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:379" - cell $and $10 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + cell $and $2 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A $7 + connect \A \select_id connect \B \capture - connect \Y $9 + connect \Y $1 end process $group_1 assign \_capture 1'0 - assign \_capture $9 + assign \_capture $1 sync init end attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:241" wire width 1 \_shift - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $11 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $eq $12 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 1'1 - parameter \Y_WIDTH 1'1 - connect \A \ir - connect \B 1'1 - connect \Y $11 - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $13 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $eq $14 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 3'100 - parameter \Y_WIDTH 1'1 - connect \A \ir - connect \B 4'1111 - connect \Y $13 - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $15 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $or $16 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 1'1 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 1'1 - parameter \Y_WIDTH 1'1 - connect \A $11 - connect \B $13 - connect \Y $15 - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $17 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $and $18 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 1'1 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 1'1 - parameter \Y_WIDTH 1'1 - connect \A \isdr - connect \B $15 - connect \Y $17 - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - wire width 1 $19 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $and $20 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + wire width 1 $3 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + cell $and $4 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A $17 + connect \A \select_id connect \B \shift - connect \Y $19 + connect \Y $3 end process $group_2 assign \_shift 1'0 - assign \_shift $19 + assign \_shift $3 sync init end attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:242" wire width 1 \_update - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $21 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $eq $22 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 1'1 - parameter \Y_WIDTH 1'1 - connect \A \ir - connect \B 1'1 - connect \Y $21 - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $23 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $eq $24 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 3'100 - parameter \Y_WIDTH 1'1 - connect \A \ir - connect \B 4'1111 - connect \Y $23 - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $25 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $or $26 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 1'1 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 1'1 - parameter \Y_WIDTH 1'1 - connect \A $21 - connect \B $23 - connect \Y $25 - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $27 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $and $28 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 1'1 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 1'1 - parameter \Y_WIDTH 1'1 - connect \A \isdr - connect \B $25 - connect \Y $27 - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:381" - wire width 1 $29 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:381" - cell $and $30 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + wire width 1 $5 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + cell $and $6 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A $27 + connect \A \select_id connect \B \update - connect \Y $29 + connect \Y $5 end process $group_3 assign \_update 1'0 - assign \_update $29 + assign \_update $5 sync init end attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:243" wire width 1 \_bypass - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:382" - wire width 1 $31 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:382" - cell $eq $32 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 - parameter \B_SIGNED 1'0 - parameter \B_WIDTH 3'100 - parameter \Y_WIDTH 1'1 - connect \A \ir - connect \B 4'1111 - connect \Y $31 - end process $group_4 assign \_bypass 1'0 - assign \_bypass $31 + assign \_bypass \id_bypass sync init end attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:236" @@ -981,10 +812,14 @@ module \jtag wire width 1 \posjtag_clk attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire width 1 \posjtag_rst - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire width 1 \_fsm_capture + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire width 1 \negjtag_clk + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire width 1 \negjtag_rst attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:23" wire width 1 \_fsm_isdr + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire width 1 \_fsm_capture attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:25" wire width 1 \_fsm_shift attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:26" @@ -992,18 +827,20 @@ module \jtag attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:22" wire width 1 \_fsm_isir cell \_fsm \_fsm - connect \capture \_fsm_capture connect \isdr \_fsm_isdr + connect \capture \_fsm_capture connect \shift \_fsm_shift connect \update \_fsm_update connect \isir \_fsm_isir connect \posjtag_rst \posjtag_rst + connect \negjtag_rst \negjtag_rst connect \posjtag_clk \posjtag_clk + connect \negjtag_clk \negjtag_clk connect \tck \tck connect \tms \tms end attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:127" - wire width 4 \_irblock_ir + wire width 3 \_irblock_ir attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire width 1 \_irblock_tdo cell \_irblock \_irblock @@ -1011,56 +848,58 @@ module \jtag connect \capture \_fsm_capture connect \shift \_fsm_shift connect \update \_fsm_update + connect \tdi \tdi connect \isir \_fsm_isir connect \tdo \_irblock_tdo - connect \tdi \tdi connect \posjtag_rst \posjtag_rst connect \posjtag_clk \posjtag_clk end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire width 1 \_idblock_select_id + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire width 1 \_idblock_id_bypass attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:225" wire width 1 \_idblock_jtag_id_tdo cell \_idblock \_idblock - connect \ir \_irblock_ir + connect \select_id \_idblock_select_id + connect \id_bypass \_idblock_id_bypass connect \capture \_fsm_capture - connect \isdr \_fsm_isdr connect \shift \_fsm_shift connect \update \_fsm_update - connect \jtag_id_tdo \_idblock_jtag_id_tdo connect \tdi \tdi + connect \jtag_id_tdo \_idblock_jtag_id_tdo connect \posjtag_rst \posjtag_rst connect \posjtag_clk \posjtag_clk end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:387" - wire width 1 \io_capture - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire width 1 $1 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:377" cell $eq $2 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 connect \A \_irblock_ir - connect \B 1'0 + connect \B 1'1 connect \Y $1 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire width 1 $3 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:377" cell $eq $4 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 - parameter \B_WIDTH 2'10 + parameter \B_WIDTH 2'11 parameter \Y_WIDTH 1'1 connect \A \_irblock_ir - connect \B 2'10 + connect \B 3'111 connect \Y $3 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire width 1 $5 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:377" cell $or $6 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 @@ -1071,143 +910,148 @@ module \jtag connect \B $3 connect \Y $5 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire width 1 $7 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:377" cell $and $8 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A $5 - connect \B \_fsm_capture + connect \A \_fsm_isdr + connect \B $5 connect \Y $7 end process $group_0 - assign \io_capture 1'0 - assign \io_capture $7 + assign \_idblock_select_id 1'0 + assign \_idblock_select_id $7 sync init end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:388" - wire width 1 \io_shift - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:378" wire width 1 $9 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:378" cell $eq $10 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 - parameter \B_WIDTH 1'1 + parameter \B_WIDTH 2'11 parameter \Y_WIDTH 1'1 connect \A \_irblock_ir - connect \B 1'0 + connect \B 3'111 connect \Y $9 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + process $group_1 + assign \_idblock_id_bypass 1'0 + assign \_idblock_id_bypass $9 + sync init + end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:391" + wire width 1 \io_capture + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire width 1 $11 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $eq $12 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 - parameter \B_WIDTH 2'10 + parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 connect \A \_irblock_ir - connect \B 2'10 + connect \B 1'0 connect \Y $11 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire width 1 $13 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" - cell $or $14 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $14 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 1'1 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 - parameter \B_WIDTH 1'1 + parameter \B_WIDTH 2'10 parameter \Y_WIDTH 1'1 - connect \A $9 - connect \B $11 + connect \A \_irblock_ir + connect \B 2'10 connect \Y $13 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire width 1 $15 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393" - cell $eq $16 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $16 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 - parameter \B_WIDTH 2'10 + parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A \_irblock_ir - connect \B 2'10 + connect \A $11 + connect \B $13 connect \Y $15 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:400" wire width 1 $17 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394" - cell $or $18 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:400" + cell $and $18 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A $13 - connect \B $15 + connect \A $15 + connect \B \_fsm_capture connect \Y $17 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + process $group_2 + assign \io_capture 1'0 + assign \io_capture $17 + sync init + end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + wire width 1 \io_shift + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire width 1 $19 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394" - cell $and $20 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $20 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 1'1 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A \_fsm_isdr - connect \B $17 + connect \A \_irblock_ir + connect \B 1'0 connect \Y $19 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire width 1 $21 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $22 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $22 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 1'1 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 - parameter \B_WIDTH 1'1 + parameter \B_WIDTH 2'10 parameter \Y_WIDTH 1'1 - connect \A $19 - connect \B \_fsm_shift + connect \A \_irblock_ir + connect \B 2'10 connect \Y $21 end - process $group_1 - assign \io_shift 1'0 - assign \io_shift $21 - sync init - end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:389" - wire width 1 \io_update - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire width 1 $23 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" - cell $eq $24 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $24 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A \_irblock_ir - connect \B 1'0 + connect \A $19 + connect \B $21 connect \Y $23 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire width 1 $25 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:397" cell $eq $26 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 parameter \B_WIDTH 2'10 parameter \Y_WIDTH 1'1 @@ -1215,9 +1059,9 @@ module \jtag connect \B 2'10 connect \Y $25 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire width 1 $27 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" cell $or $28 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 @@ -1228,205 +1072,378 @@ module \jtag connect \B $25 connect \Y $27 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire width 1 $29 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393" - cell $eq $30 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $30 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 - parameter \B_WIDTH 2'10 + parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A \_irblock_ir - connect \B 2'10 + connect \A \_fsm_isdr + connect \B $27 connect \Y $29 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:402" wire width 1 $31 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394" - cell $or $32 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:402" + cell $and $32 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A $27 - connect \B $29 + connect \A $29 + connect \B \_fsm_shift connect \Y $31 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + process $group_3 + assign \io_shift 1'0 + assign \io_shift $31 + sync init + end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393" + wire width 1 \io_update + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire width 1 $33 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394" - cell $and $34 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $34 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 1'1 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A \_fsm_isdr - connect \B $31 + connect \A \_irblock_ir + connect \B 1'0 connect \Y $33 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:399" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire width 1 $35 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:399" - cell $and $36 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $36 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 2'11 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 2'10 + parameter \Y_WIDTH 1'1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $35 + end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire width 1 $37 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $38 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 connect \A $33 + connect \B $35 + connect \Y $37 + end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + wire width 1 $39 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $40 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 2'11 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 2'10 + parameter \Y_WIDTH 1'1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $39 + end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire width 1 $41 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $42 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $37 + connect \B $39 + connect \Y $41 + end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire width 1 $43 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $44 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \_fsm_isdr + connect \B $41 + connect \Y $43 + end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + wire width 1 $45 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + cell $and $46 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $43 connect \B \_fsm_update - connect \Y $35 + connect \Y $45 end - process $group_2 + process $group_4 assign \io_update 1'0 - assign \io_update $35 + assign \io_update $45 sync init end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:390" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394" wire width 1 \io_bd2io - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - wire width 1 $37 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - cell $eq $38 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + wire width 1 $47 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + cell $eq $48 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $37 + connect \Y $47 end - process $group_3 + process $group_5 assign \io_bd2io 1'0 - assign \io_bd2io $37 + assign \io_bd2io $47 sync init end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:391" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:395" wire width 1 \io_bd2core - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:401" - wire width 1 $39 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:401" - cell $eq $40 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + wire width 1 $49 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + cell $eq $50 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $39 + connect \Y $49 end - process $group_4 + process $group_6 assign \io_bd2core 1'0 - assign \io_bd2core $39 + assign \io_bd2core $49 + sync init + end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 1 \io_sr + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 1 \io_sr$next + attribute \src "add.py:32" + wire width 1 \test__pad__i + process $group_7 + assign \io_sr$next \io_sr + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + case 3'--1 + assign \io_sr$next { \test__pad__i } + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:570" + case 3'-1- + assign \io_sr$next { {} \tdi } + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:574" + case 3'1-- + end + attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530" + switch \posjtag_rst + case 1'1 + assign \io_sr$next 1'0 + end + sync init + update \io_sr 1'0 + sync posedge \posjtag_clk + update \io_sr \io_sr$next + end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 1 \io_bd + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 1 \io_bd$next + process $group_8 + assign \io_bd$next \io_bd + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + case 3'--1 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:570" + case 3'-1- + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:574" + case 3'1-- + assign \io_bd$next \io_sr + end + attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530" + switch \negjtag_rst + case 1'1 + assign \io_bd$next 1'0 + end + sync init + update \io_bd 1'0 + sync negedge \negjtag_clk + update \io_bd \io_bd$next + end + attribute \src "add.py:32" + wire width 1 \test__core__i + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire width 1 $51 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $52 + parameter \WIDTH 1'1 + connect \A \test__pad__i + connect \B \io_bd + connect \S \io_bd2core + connect \Y $51 + end + process $group_9 + assign \test__core__i 1'0 + assign \test__core__i $51 sync init end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:410" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:414" wire width 1 \jtag_tdo - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $41 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $eq $42 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire width 1 $53 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $54 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 connect \A \_irblock_ir - connect \B 1'1 - connect \Y $41 + connect \B 1'0 + connect \Y $53 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $43 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $eq $44 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire width 1 $55 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $56 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 - parameter \B_WIDTH 3'100 + parameter \B_WIDTH 2'10 parameter \Y_WIDTH 1'1 connect \A \_irblock_ir - connect \B 4'1111 - connect \Y $43 + connect \B 2'10 + connect \Y $55 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $45 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $or $46 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire width 1 $57 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $58 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A $41 - connect \B $43 - connect \Y $45 + connect \A $53 + connect \B $55 + connect \Y $57 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire width 1 $47 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - cell $and $48 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + wire width 1 $59 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $60 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 2'11 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 2'10 + parameter \Y_WIDTH 1'1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $59 + end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire width 1 $61 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $62 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $57 + connect \B $59 + connect \Y $61 + end + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire width 1 $63 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $64 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 connect \A \_fsm_isdr - connect \B $45 - connect \Y $47 + connect \B $61 + connect \Y $63 end - process $group_5 + process $group_10 assign \jtag_tdo 1'0 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:411" - switch { $47 \_fsm_isir } - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:411" - case 2'-1 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:415" + switch { $63 \_idblock_select_id \_fsm_isir } + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:415" + case 3'--1 assign \jtag_tdo \_irblock_tdo - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:413" - case 2'1- + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:417" + case 3'-1- assign \jtag_tdo \_idblock_jtag_id_tdo + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:420" + case 3'1-- + assign \jtag_tdo \io_sr end sync init end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:638" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 3 \sr0_reg - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:638" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 3 \sr0_reg$next - process $group_6 + process $group_11 assign \sr0__o 3'000 assign \sr0__o \sr0_reg sync init end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:641" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire width 1 \sr0_isir - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire width 1 $49 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - cell $eq $50 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire width 1 $65 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $66 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 3'100 + parameter \A_WIDTH 2'11 parameter \B_SIGNED 1'0 parameter \B_WIDTH 2'11 parameter \Y_WIDTH 1'1 connect \A \_irblock_ir connect \B 3'100 - connect \Y $49 + connect \Y $65 end - process $group_7 + process $group_12 assign \sr0_isir 1'0 - assign \sr0_isir { $49 } + assign \sr0_isir { $65 } sync init end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire width 1 \sr0_capture - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire width 1 $51 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - cell $ne $52 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire width 1 $67 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $68 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 @@ -1434,32 +1451,32 @@ module \jtag parameter \Y_WIDTH 1'1 connect \A \sr0_isir connect \B 1'0 - connect \Y $51 + connect \Y $67 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire width 1 $53 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - cell $and $54 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire width 1 $69 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $70 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A $51 + connect \A $67 connect \B \_fsm_capture - connect \Y $53 + connect \Y $69 end - process $group_8 + process $group_13 assign \sr0_capture 1'0 - assign \sr0_capture $53 + assign \sr0_capture $69 sync init end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:643" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire width 1 \sr0_shift - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire width 1 $55 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - cell $ne $56 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire width 1 $71 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $72 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 @@ -1467,32 +1484,32 @@ module \jtag parameter \Y_WIDTH 1'1 connect \A \sr0_isir connect \B 1'0 - connect \Y $55 + connect \Y $71 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire width 1 $57 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - cell $and $58 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire width 1 $73 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $74 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A $55 + connect \A $71 connect \B \_fsm_shift - connect \Y $57 + connect \Y $73 end - process $group_9 + process $group_14 assign \sr0_shift 1'0 - assign \sr0_shift $57 + assign \sr0_shift $73 sync init end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:644" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648" wire width 1 \sr0_update - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:649" - wire width 1 $59 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:649" - cell $ne $60 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire width 1 $75 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $76 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 @@ -1500,31 +1517,31 @@ module \jtag parameter \Y_WIDTH 1'1 connect \A \sr0_isir connect \B 1'0 - connect \Y $59 + connect \Y $75 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:649" - wire width 1 $61 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:649" - cell $and $62 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire width 1 $77 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $78 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 - connect \A $59 + connect \A $75 connect \B \_fsm_update - connect \Y $61 + connect \Y $77 end - process $group_10 + process $group_15 assign \sr0_update 1'0 - assign \sr0_update $61 + assign \sr0_update $77 sync init end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:656" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire width 1 \sr0_update_core - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:656" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire width 1 \sr0_update_core$next - process $group_11 + process $group_16 assign \sr0_update_core$next \sr0_update_core assign \sr0_update_core$next \sr0_update attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530" @@ -1537,11 +1554,11 @@ module \jtag sync posedge \clk update \sr0_update_core \sr0_update_core$next end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:657" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire width 1 \sr0_update_core_prev - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:657" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire width 1 \sr0_update_core_prev$next - process $group_12 + process $group_17 assign \sr0_update_core_prev$next \sr0_update_core_prev assign \sr0_update_core_prev$next \sr0_update_core attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530" @@ -1558,37 +1575,37 @@ module \jtag wire width 1 \sr0__oe attribute \src "add.py:29" wire width 1 \sr0__oe$next - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663" - wire width 1 $63 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663" - cell $not $64 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire width 1 $79 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $80 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \Y_WIDTH 1'1 connect \A \sr0_update_core - connect \Y $63 + connect \Y $79 end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663" - wire width 1 $65 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663" - cell $and $66 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire width 1 $81 + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $82 parameter \A_SIGNED 1'0 parameter \A_WIDTH 1'1 parameter \B_SIGNED 1'0 parameter \B_WIDTH 1'1 parameter \Y_WIDTH 1'1 connect \A \sr0_update_core_prev - connect \B $63 - connect \Y $65 + connect \B $79 + connect \Y $81 end - process $group_13 + process $group_18 assign \sr0__oe$next \sr0__oe - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663" - switch { $65 } - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch { $81 } + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:667" case 1'1 assign \sr0__oe$next \sr0_isir - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:666" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:670" case assign \sr0__oe$next 1'0 end @@ -1602,17 +1619,17 @@ module \jtag sync posedge \clk update \sr0__oe \sr0__oe$next end - process $group_14 + process $group_19 assign \sr0_reg$next \sr0_reg - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:669" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:673" switch { \sr0_shift } - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:669" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:673" case 1'1 assign \sr0_reg$next { \tdi \sr0_reg [2:1] } end - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:671" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch { \sr0_capture } - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:671" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:675" case 1'1 assign \sr0_reg$next \sr0__i end @@ -1626,19 +1643,20 @@ module \jtag sync posedge \posjtag_clk update \sr0_reg \sr0_reg$next end - process $group_15 + process $group_20 assign \tdo 1'0 - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:681" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:685" switch { \sr0_shift } - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:681" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:685" case 1'1 assign \tdo \sr0_reg [0] - attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:688" + attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:692" case assign \tdo \jtag_tdo end sync init end + connect \test__pad__i 1'0 end attribute \generator "nMigen" attribute \top 1 @@ -1683,11 +1701,11 @@ module \add assign \jtag_sr0__i \jtag_sr0__o sync init end - attribute \src "add.py:38" + attribute \src "add.py:41" wire width 5 $1 - attribute \src "add.py:38" + attribute \src "add.py:41" wire width 5 $2 - attribute \src "add.py:38" + attribute \src "add.py:41" cell $add $3 parameter \A_SIGNED 1'0 parameter \A_WIDTH 3'100 -- 2.30.2