From 35a723b989e07f6b08c7b9e79dbe23fee33c30fb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 14 Dec 2021 17:02:10 +0000 Subject: [PATCH] get OP_FETCH_FAILED to respond/return an exception correctly --- src/soc/fu/ldst/loadstore.py | 1 + src/soc/fu/mmu/fsm.py | 4 +--- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index ad4d78f2..080d3320 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -292,6 +292,7 @@ class LoadStore1(PortInterfaceBase): # TODO: critical that the write here has to # notify the MMU FSM of the change to dsisr comb += exception.eq(1) + comb += self.done.eq(1) sync += Display("MMU RADIX exception thrown") sync += Display("TODO: notify MMU of change to dsisr") sync += self.dsisr[63 - 33].eq(m_in.invalid) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index 752f7ef6..e1f2b2ee 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -227,9 +227,7 @@ class FSMMMUStage(ControlBase): comb += ldst.priv_mode.eq(~msr_i[MSR.PR]) comb += ldst.maddr.eq(nia_i) # XXX should not access this! - mmu_done_delay = Signal() - sync += mmu_done_delay.eq(mmu.d_in.done) - comb += done.eq(mmu_done_delay) + comb += done.eq(ldst.done) comb += self.debug0.eq(3) # LDST unit contains exception data, which (messily) # is copied over, here. not ideal but it will do for now -- 2.30.2