From 35ae672cec8f76d7c8ba8043953e66fa7668e5e3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 12 Oct 2018 16:15:32 +0100 Subject: [PATCH] add RS3 replacement --- riscv/sv_insn_redirect.cc | 5 +++++ riscv/sv_insn_redirect.h | 14 +++----------- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index f0759bc..283543a 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -23,6 +23,11 @@ reg_t sv_proc_t::get_rs2() return insn->p->get_state()->XPR[insn->rs2()]; } +reg_t sv_proc_t::get_rs3() +{ + return insn->p->get_state()->XPR[insn->rs3()]; +} + freg_t sv_proc_t::get_frs1() { return READ_FREG(insn->rs1()); diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h index cb4848a..64338e0 100644 --- a/riscv/sv_insn_redirect.h +++ b/riscv/sv_insn_redirect.h @@ -7,25 +7,16 @@ #undef RS1 #undef RS2 +#undef RS3 #undef FRS1 class processor_t; class insn_t; -/* -class FRS1 { - public: - sv_insn_t *_insn; - FRS1() : _insn(NULL) {} - //sv_insn_t & operator = (sv_insn_t &i) - //{ _insn = &i; return i; } - operator freg_t () const &; -}; -*/ - #define FRS1 get_frs1() #define RS1 get_rs1() #define RS2 get_rs2() +#define RS3 get_rs3() /* class RS2 { @@ -54,6 +45,7 @@ public: reg_t get_rs1(); reg_t get_rs2(); + reg_t get_rs3(); freg_t get_frs1(); -- 2.30.2