From 35e38590aa0bfc2c5b3926d6bdaaa677a9c7226f Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 30 Dec 2020 16:44:47 +0000 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 668d17467..94b461769 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -264,6 +264,8 @@ elwidth, because these ops are pure explicit CR based. Examples: mfxm may take the extra bits and use them as extra mask bits. +Example: hypothetically, operations could be modified to be considered 2-bit or 1-bit per CR. This would need a very comprehensive review. + # SUBVL Encoding the default for SUBVL is 1 and its encoding is 0b00 to indicate that -- 2.30.2