From 35f31c2b1e1da74bdeb1aece5a9643e3367fc337 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 12 Mar 2021 12:00:58 +0000 Subject: [PATCH] decoding of svp64 reg by name has to occur after immediate is extracted otherwise tries to identify D(RA) as a GPR which of course fails --- src/soc/sv/trans/svp64.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py index 27ec7bea..7957771f 100644 --- a/src/soc/sv/trans/svp64.py +++ b/src/soc/sv/trans/svp64.py @@ -215,8 +215,8 @@ class SVP64Asm: # now for each of those find its place in the EXTRA encoding extras = OrderedDict() for idx, (field, regname) in enumerate(opregfields): - extra = svp64_reg_byname.get(regname, None) imm, regname = decode_imm(regname) + extra = svp64_reg_byname.get(regname, None) rtype = get_regtype(regname) extras[extra] = (idx, field, regname, rtype, imm) print (" ", extra, extras[extra]) @@ -239,7 +239,8 @@ class SVP64Asm: immed, field = field[:-1].split("(") field, regmode = decode_reg(field) - print (" ", rtype, regmode, iname, field, end=" ") + print (" ", extra_idx, rname, rtype, + regmode, iname, field, end=" ") # see Mode field https://libre-soc.org/openpower/sv/svp64/ # XXX TODO: the following is a bit of a laborious repeated @@ -609,7 +610,8 @@ if __name__ == '__main__': 'sv.add. 5.v, 2.v, 1.v', ] lst += [ - 'sv.ld 5.v, 4(4.v)', + 'sv.stw 5.v, 4(1.v)', + 'sv.ld 5.v, 4(1.v)', ] isa = SVP64Asm(lst) print ("list", list(isa)) -- 2.30.2