From 36107cdfd79752289b24fb6200a90094d78ad597 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 20 Nov 2019 19:24:40 +0100 Subject: [PATCH] soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal --- litex/soc/cores/clock.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index 70133f39..e1964555 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -225,7 +225,7 @@ class S7PLL(XilinxClocking): config = self.compute_config() pll_fb = Signal() self.params.update( - p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, + p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset, # VCO p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq, @@ -319,7 +319,7 @@ class USPLL(XilinxClocking): config = self.compute_config() pll_fb = Signal() self.params.update( - p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, + p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset, # VCO p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq, @@ -355,7 +355,7 @@ class USMMCM(XilinxClocking): config = self.compute_config() mmcm_fb = Signal() self.params.update( - p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, + p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset, # VCO p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq, -- 2.30.2