From 362bfea26aa57a97b3a10717661a18c2d49fde9c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 19 Jun 2019 16:03:32 +0100 Subject: [PATCH] add SV VLIW idea --- simple_v_extension/specification.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index bbed33931..a6ea3e874 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -2233,7 +2233,7 @@ Reminder of the variable-length format from Section 1.5 of the RISC-V ISA: | base+4 | base+2 | base | number of bits | | ------ | ---------------- | ---------------- | -------------------------- | | ..xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 | -| {ops}{Pred}{Reg}{VL} || SV Prefix | | +|| {ops}{Pred}{Reg}{VL} | SV Prefix | | Notes: -- 2.30.2