From 36398347c24aaced5dd91309575526c89fedd74e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 19 May 2020 21:33:38 +0100 Subject: [PATCH] use Data on SPRs in Trap InputData just like in BranchOutputData --- src/soc/fu/trap/main_stage.py | 6 ++++-- src/soc/fu/trap/pipe_data.py | 6 +++--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 275d1aa1..db688475 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -84,9 +84,11 @@ class LogicalMainStage(PipeModBase): with m.Case(InternalOp.OP_TRAP): with m.If(should_trap): comb += self.o.nia.eq(0x700) # trap address - comb += self.o.srr1.eq(self.i.msr) # old MSR + comb += self.o.srr1.data.eq(self.i.msr) # old MSR comb += self.o.srr1[63-46].eq(1) # XXX which bit? - comb += self.o.srr0.eq(self.i.cia) # old PC + comb += self.o.srr1.ok.eq(1) + comb += self.o.srr0.data.eq(self.i.cia) # old PC + comb += self.o.srr0.ok.eq(1) comb += self.o.ctx.eq(self.i.ctx) comb += self.o.should_trap.eq(should_trap) diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py index 581040c4..83adc38a 100644 --- a/src/soc/fu/trap/pipe_data.py +++ b/src/soc/fu/trap/pipe_data.py @@ -1,7 +1,7 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext from soc.fu.alu.pipe_data import IntegerData - +from soc.decoder.power_decoder2 import Data class TrapInputData(IntegerData): def __init__(self, pspec): @@ -28,8 +28,8 @@ class TrapOutputData(IntegerData): super().__init__(pspec) self.nia = Signal(64, reset_less=True) # NIA (Next PC) self.msr = Signal(64, reset_less=True) # MSR - self.srr0 = Signal(64, reset_less=True) # SRR0 SPR - self.srr1 = Signal(64, reset_less=True) # SRR1 SPR + self.srr0 = Data(64, name="srr0") # SRR0 SPR + self.srr1 = Data(64, name="srr1") # SRR1 SPR self.should_trap = Signal(reset_less=True) def __iter__(self): -- 2.30.2