From 363badab20b5c32c4ce6c69734fa4a37b3dad94d Mon Sep 17 00:00:00 2001
From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sat, 17 Sep 2022 23:42:48 +0300
Subject: [PATCH] pysvp64asm: SVP64 instruction debug logs

---
 src/openpower/sv/trans/svp64.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index b6944855..7f0b880c 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1462,6 +1462,8 @@ class SVP64Asm:
             if not v30b_op.endswith('.'):
                 v30b_op += rc
             yield "%s %s" % (v30b_op, ", ".join(v30b_newfields))
+        for (field, value, span) in svp64_insn.traverse("SVP64"):
+            log(field, f"{value.value:0{value.bits}b}", span)
         log("new v3.0B fields", v30b_op, v30b_newfields)
 
     def translate(self, lst):
-- 
2.30.2