From 36456ca03586c69e8f213a7a041377d082eef9de Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 15 May 2020 12:18:25 +0100 Subject: [PATCH] cool! countzero unit test works! --- src/soc/countzero/test/test_countzero.py | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/soc/countzero/test/test_countzero.py b/src/soc/countzero/test/test_countzero.py index 3647cb4d..538db15c 100644 --- a/src/soc/countzero/test/test_countzero.py +++ b/src/soc/countzero/test/test_countzero.py @@ -13,7 +13,7 @@ class ZeroCounterTestCase(FHDLTestCase): m.submodules.dut = dut = ZeroCounter() sim = Simulator(m) - sim.add_clock(1e-6) + # sim.add_clock(1e-6) def process(): print("test zero input") @@ -43,6 +43,18 @@ class ZeroCounterTestCase(FHDLTestCase): assert(result == 0x20) # TODO next tests + yield dut.rs_i.eq(0b00010000) + yield dut.is_32bit_i.eq(0) + yield dut.count_right_i.eq(0) + yield Delay(1e-6) + result = yield dut.result_o + assert result == 4, "result %d" % result + + yield dut.count_right_i.eq(1) + yield Delay(1e-6) + result = yield dut.result_o + assert result == 59, "result %d" % result + sim.add_process(process) # or sim.add_sync_process(process), see below # run test and write vcd -- 2.30.2