From 36513a688e55d8f7f102064c418b52657bab843b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Jun 2020 21:20:37 +0100 Subject: [PATCH] add debug print statements, re-enable all tests in simple core --- src/soc/fu/cr/test/test_pipe_caller.py | 4 +++- src/soc/simple/test/test_core.py | 12 ++++++------ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index 82685432..7bf1e260 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -223,9 +223,11 @@ class TestRunner(FHDLTestCase): self.assertEqual(expected_cr, full_cr, code) elif cr_en: cr_sel = yield dec2.e.write_cr.data + expected_cr = simulator.cr.get_range().value + print(f"CR whole: {expected_cr:x}, sel {cr_sel}") expected_cr = simulator.crl[cr_sel].get_range().value real_cr = yield alu.n.data_o.cr.data - print(f"CR whole: expected {expected_cr:x}, actual: {real_cr:x}") + print(f"CR part: expected {expected_cr:x}, actual: {real_cr:x}") self.assertEqual(expected_cr, real_cr, code) alu_out = yield alu.n.data_o.o.data out_reg_valid = yield dec2.e.write_reg.ok diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index cd8ca928..a1e94ba9 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -169,8 +169,8 @@ class TestRunner(FHDLTestCase): cri = sim.crl[7-i].get_range().value print ("cr reg", i, hex(cri), i, hex(rval)) # XXX https://bugs.libre-soc.org/show_bug.cgi?id=363 - #self.assertEqual(cri, rval, - # "cr reg %d not equal %s" % (i, repr(code))) + self.assertEqual(cri, rval, + "cr reg %d not equal %s" % (i, repr(code))) sim.add_sync_process(process) with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw", @@ -182,10 +182,10 @@ if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() suite.addTest(TestRunner(CRTestCase.test_data)) - #suite.addTest(TestRunner(ShiftRotTestCase.test_data)) - #suite.addTest(TestRunner(LogicalTestCase.test_data)) - #suite.addTest(TestRunner(ALUTestCase.test_data)) - #suite.addTest(TestRunner(BranchTestCase.test_data)) + suite.addTest(TestRunner(ShiftRotTestCase.test_data)) + suite.addTest(TestRunner(LogicalTestCase.test_data)) + suite.addTest(TestRunner(ALUTestCase.test_data)) + suite.addTest(TestRunner(BranchTestCase.test_data)) runner = unittest.TextTestRunner() runner.run(suite) -- 2.30.2